mt47h64m16hw-3 Micron Semiconductor Products, mt47h64m16hw-3 Datasheet - Page 41

• Manufacturer Part Number: mt47h64m16hw-3
• Description: 1gb X4, X8, X16 Ddr2 Sdram
• Manufacturer: Micron Semiconductor Products

AC and DC Operating Conditions
Table 14:
PDF: 09005aef8117c187/Source: 09005aef821aed36
DDR2_x4x8x16_Core2.fm - 1Gb DDR2: Rev. N; Core DDR2: Rev. C 4/08 EN
Parameter
Supply voltage
V
I/O supply voltage
I/O reference voltage
I/O termination voltage (system)
DD
L supply voltage
Recommended DC Operating Conditions (SSTL_18)
All voltages referenced to V
Notes:
42.
43.
44.
45. The half-clock of
46. ODT turn-on time
47. ODT turn-off time
48. Half-clock output parameters must be derated by the actual
49. The -187E maximum limit is 2 ×
50. Should use 8
1. V
2. V
3. V
4. V
5. V
t
prior to CK, CK# being removed in a system RESET condition (see "Reset" on page
118).
t
Figure 70 on page 109.
t
tive clock edges. CKE must remain at the valid input level the entire time it takes to
achieve the three clocks of registration. Thus, after any CKE transition, CKE may not
transition from its valid level during the time period of
value must be derated by the amount of half-clock duty cycle error. For example, if the
clock duty cycle was 47/53,
and 2.5 + 0.03, or 2.53, for
begins to turn on. ODT turn-on time
on. Both are measured from
ODT turn off time
t
when input clock jitter is present; this will result in each parameter becoming larger.
The parameter
t
ated by subtracting both
3 x
DC level of the same. Peak-to-peak noise (noncommon mode) on V
percent of the DC value. Peak-to-peak AC noise on V
V
tors, is expected to be set equal to V
DELAY is calculated from
ISXR is equal to
CKE (MIN) of three clocks means CKE must be registered on three consecutive posi-
AOFD.
ERR
DD
SS
DD
REF
REF
TT
t
Q = V
CK +
Q tracks with V
is not applied directly to the device. V
(
and V
5
is expected to equal V
DC
PER
). This measurement is to be taken at the nearest V
SS
(MAX) and
t
AC (MAX) + 1,000 in the future.
SS
DD
L = V
Q must track each other. V
t
CK for backward compatibility.
SS
Symbol
V
t
AOF (MIN) is required to be derated by subtracting both
V
.
t
REF
V
IS and is used for CKE setup time during self refresh exit, as shown in
V
t
V
DD
DD
AOFD’s 2.5
DD
DD
t
TT
t
t
AOF (MAX) is when the bus is in High-Z. Both are measured from
(
AON (MIN) is when the device leaves High-Z and ODT resistance
AOF (MIN) is when the device starts to turn off ODT resistance.
DC
Q
t
L
; V
JIT
)
DD
DTY
t
L tracks with V
DD
ERR
t
t
AOF (MAX).
41
IS +
0.49 × V
V
t
Q/2 of the transmitting device and to track variations in the
(MAX). The parameter
AOFD would actually be 2.5 - 0.03, or 2.47, for
t
REF
AOND.
t
5
CK assumes a 50/50 clock duty cycle. This half-clock
PER
Min
(
t
1.7
1.7
1.7
CK +
DC
t
CK +
(MIN) and
) - 40
REF
DD
Micron Technology, Inc., reserves the right to change products or specifications without notice.
, and must track variations in the DC level of V
DD
Q
t
t
AON (MAX) is when the ODT resistance is fully
IH so that CKE registration LOW is guaranteed
t
AC (MAX) + 1,000 but it will likely be
DD
Q must be ≤ V
TT
.
is a system supply for signal termination resis-
0.50 × V
AC and DC Operating Conditions
V
t
Nom
REF
JIT
1.8
1.8
1.8
1Gb: x4, x8, x16 DDR2 SDRAM
(
DTY
DC
DD
REF
t
)
AOF (MAX) is required to be der-
Q
(MIN).
DD
may not exceed ±2 percent of
REF
.
t
IS + 2 ×
V
0.51 × V
REF
bypass capacitor.
©2003 Micron Technology, Inc. All rights reserved.
Max
(
t
1.9
1.9
1.9
DC
ERR
REF
) + 40
t
CK +
DD
5
may not exceed ±1
PER
Q
t
and
IH.
Units
mV
V
V
V
V
t
t
AOF (MIN)
JIT
DTY
Notes
2, 3
2, 3
1, 2
REF
5
4
.