mt47h64m16hw-3 Micron Semiconductor Products, mt47h64m16hw-3 Datasheet - Page 70

• Manufacturer Part Number: mt47h64m16hw-3
• Description: 1gb X4, X8, X16 Ddr2 Sdram
• Manufacturer: Micron Semiconductor Products

Table 41:
DESELECT
NO OPERATION (NOP)
PDF: 09005aef8117c187/Source: 09005aef821aed36
DDR2_x4x8x16_Core2.fm - 1Gb DDR2: Rev. N; Core DDR2: Rev. C 4/08 EN
Minimum Delay with Auto Precharge Enabled
10. The number of clock cycles required to meet
4. REFRESH and LOAD MODE commands may only be issued when all banks are idle.
5. Not used.
6. All states and sequences not shown are illegal or reserved.
7. READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto
8. A WRITE command may be applied after the completion of the READ burst.
9. Requires appropriate DM.
The DESELECT function (CS# HIGH) prevents new commands from being executed by
the DDR2 SDRAM. The DDR2 SDRAM is effectively deselected. Operations already in
progress are not affected. DESELECT is also referred to as COMMAND INHIBIT.
The NO OPERATION (NOP) command is used to instruct the selected DDR2 SDRAM to
perform a NOP (CS# is LOW; RAS#, CAS#, and WE are HIGH). This prevents unwanted
commands from being registered during idle or wait states. Operations already in
progress are not affected.
From Command
WRITE with auto
READ with auto
READ with
auto
precharge
enabled/
WRITE with
auto
precharge
enabled:
The minimum delay from a READ or WRITE command with auto precharge enabled to a
command to a different bank is summarized in Table 41:
precharge enabled and READs or WRITEs with auto precharge disabled.
greater.
precharge
precharge
(Bank n)
The READ with auto precharge enabled or WRITE with auto precharge
enabled states can each be broken into two parts: the access period and the
precharge period. For READ with auto precharge, the precharge period is
defined as if the same burst was executed with auto precharge disabled and
then followed with the earliest possible PRECHARGE command that still
accesses all of the data in the burst. For WRITE with auto precharge, the
precharge period begins when
precharge was disabled. The access period starts with registration of the
command and ends where the precharge period (or
supports concurrent auto precharge such that when a READ with auto
precharge is enabled or a WRITE with auto precharge is enabled, any
command to other banks is allowed, as long as that command does not
interrupt the read or write data transfer already in process. In either case, all
other related limitations apply (contention between read data and write
data must be avoided).
WRITE or WRITE with auto
WRITE or WRITE with auto
PRECHARGE or ACTIVATE
PRECHARGE or ACTIVATE
To Command (Bank m)
READ or READ with auto
READ or READ with auto
precharge
precharge
precharge
precharge
70
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
t
WTR is either two or
WR ends, with
1Gb: x4, x8, x16 DDR2 SDRAM
(CL - 1) + (BL/2) +
(with Concurrent
Auto Precharge)
Minimum Delay
t
WR measured as if auto
(BL/2) + 2
©2003 Micron Technology, Inc. All rights reserved.
(BL/2)
(BL/2)
1
1
t
t
RP) begins. This device
WTR/
t
t
CK, whichever is
WTR
Commands
Units
t
t
t
t
t
t
CK
CK
CK
CK
CK
CK