mt47h64m16hw-3 Micron Semiconductor Products, mt47h64m16hw-3 Datasheet - Page 91

• Manufacturer Part Number: mt47h64m16hw-3
• Description: 1gb X4, X8, X16 Ddr2 Sdram
• Manufacturer: Micron Semiconductor Products

DQS, DQS#
Figure 51:
READ with Precharge
Figure 52:
PDF: 09005aef8117c187/Source: 09005aef821aed36
DDR2_x4x8x16_Core2.fm - 1Gb DDR2: Rev. N; Core DDR2: Rev. C 4/08 EN
Command
CK#
DQ
CK
ACT n
T0
READ-to-WRITE
READ-to-PRECHARGE – BL = 4
Notes:
Notes:
READ n
T1
t RCD = 3
DQS, DQS#
Command
Address
1. BL = 4; CL = 3; AL = 2.
2. Shown with nominal
A READ burst may be followed by a PRECHARGE command to the same bank, provided
auto precharge is not activated. The minimum READ-to-PRECHARGE command
spacing to the same bank has two requirements that must be satisfied: AL + BL/2 clocks
and
prefetch of a READ command to the PRECHARGE command. For BL = 4, this is the time
from the actual READ (AL after the READ command) to PRECHARGE command. For
BL = 8, this is the time from AL + 2 × CK after the READ-to-PRECHARGE command.
Following the PRECHARGE command, a subsequent command to the same bank
cannot be issued until
during the access of the last data elements.
Examples of READ-to-PRECHARGE for BL = 4 are shown in Figure 52 and in Figure 53 on
page 92 for BL = 8. The delay from READ-to-PRECHARGE period to the same bank is
AL + BL/2 - 2CK + MAX (
1. RL = 4 (AL = 1, CL = 3); BL = 4.
2.
3. Shown with nominal
AL = 2
CK#
A10
NOP
DQ
CK
T2
t
RTP ≥ 2 clocks.
t
RTP .
Bank a
READ
T0
t
RTP is the minimum time from the rising clock edge that initiates the last 4-bit
AL + BL/2 - 2CK + MAX ( t RTP/ t CK or 2CK)
NOP
T3
AL = 1
RL = 5
prefetch
4-bit
≥ t RAS (MIN)
NOP
T1
NOP
T4
t
t
t
RP is met. However, part of the row precharge time is hidden
AC,
AC,
CL = 3
t
RTP/
≥ t RTP (MIN)
t
t
DQSCK, and
DQSCK, and
NOP
WRITE
T2
91
T5
t
CK or 2 × CK) where MAX means the larger of the two.
CL = 3
≥ t RC (MIN)
Bank a
NOP
Valid
T6
PRE
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T3
t
t
DQSQ.
DQSQ.
DO
n
n + 1
WL = RL - 1 = 4
DO
NOP
T7
1Gb: x4, x8, x16 DDR2 SDRAM
NOP
T4
n + 2
DO
≥ t RP (MIN)
DO
n + 3
DO
NOP
DO
T8
NOP
T5
Transitioning Data
DO
©2003 Micron Technology, Inc. All rights reserved.
Transitioning Data
NOP
T9
DI
n
DO
Bank a
Valid
ACT
T6
n + 1
DI
Operations
NOP
n + 2
T10
DI
Don’t Care
n + 3
NOP
DI
Don’t Care
T7
NOP
T11