mt47h64m16hw-3 Micron Semiconductor Products, mt47h64m16hw-3 Datasheet - Page 82

• Manufacturer Part Number: mt47h64m16hw-3
• Description: 1gb X4, X8, X16 Ddr2 Sdram
• Manufacturer: Micron Semiconductor Products

Output Drive Strength
DQS# Enable/Disable
RDQS Enable/Disable
Output Enable/Disable
On-Die Termination (ODT)
PDF: 09005aef8117c187/Source: 09005aef821aed36
DDR2_x4x8x16_Core2.fm - 1Gb DDR2: Rev. N; Core DDR2: Rev. C 4/08 EN
Anytime the DLL is disabled and the device is operated below 25 MHz, any AUTO
REFRESH command should be followed by a PRECHARGE ALL command.
The output drive strength is defined by bit E1, as shown in Figure 40 on page 81. The
normal drive strength for all outputs is specified to be SSTL_18. Programming bit E1 = 0
selects normal (full strength) drive strength for all outputs. Selecting a reduced drive
strength option (E1 = 1) will reduce all outputs to approximately 45 to 60 percent of the
SSTL_18 drive strength. This option is intended for the support of lighter load and/or
point-to-point environments.
The DQS# ball is enabled by bit E10. When E10 = 0, DQS# is the complement of the
differential data strobe pair DQS/DQS#. When disabled (E10 = 1), DQS is used in a
single-ended mode and the DQS# ball is disabled. When disabled, DQS# should be left
floating. This function is also used to enable/disable RDQS#. If RDQS is enabled
(E11 = 1) and DQS# is enabled (E10 = 0), then both DQS# and RDQS# will be enabled.
The RDQS ball is enabled by bit E11, as shown in Figure 40 on page 81. This feature is
only applicable to the x8 configuration. When enabled (E11 = 1), RDQS is identical in
function and timing to data strobe DQS during a READ. During a WRITE operation,
RDQS is ignored by the DDR2 SDRAM.
The OUTPUT ENABLE function is defined by bit E12, as shown in Figure 40 on page 81.
When enabled (E12 = 0), all outputs (DQ, DQS, DQS#, RDQS, RDQS#) function normally.
When disabled (E12 = 1), all outputs (DQ, DQS, DQS#, RDQS, RDQS#) are disabled, thus
removing output buffer current. The output disable feature is intended to be used
during I
ODT effective resistance, R
Figure 40 on page 81. The ODT feature is designed to improve signal integrity of the
memory channel by allowing the DDR2 SDRAM controller to independently turn on/off
ODT for any or all devices. R
selectable and apply to each DQ, DQS/DQS#, RDQS/RDQS#, UDQS/UDQS#, LDQS/
LDQS#, DM, and UDM/LDM signals. Bits (E6, E2) determine what ODT resistance is
enabled by turning on/off “sw1,” “sw2,” or “sw3.” The ODT effective resistance value is
selected by enabling switch “sw1,” which enables all R1 values that are 150Ω each,
enabling an effective resistance of 75Ω (R
all R2 values that are 300Ω each, enable an effective ODT resistance of 150Ω
(R
tance of 50Ω. Reserved states should not be used, as an unknown operation or incom-
patibility with future versions may result.
The ODT control ball is used to determine when R
assuming ODT has been enabled via bits E2 and E6 of the EMR. The ODT feature and
ODT input ball are only used during active, active power-down (both fast-exit and slow-
exit modes), and precharge power-down modes of operation.
TT
2
[
EFF
DD
]
characterization of read current.
= R2/2). Switch “sw3” enables R1 values of 100Ω, enabling effective resis-
TT
TT
(EFF), is defined by bits E2 and E6 of the EMR, as shown in
82
effective resistance values of 50Ω, 75Ω, and 150Ω are
Micron Technology, Inc., reserves the right to change products or specifications without notice.
TT
2
[
EFF
1Gb: x4, x8, x16 DDR2 SDRAM
]
TT
= R2/2). Similarly, if “sw2” is enabled,
(EFF) is turned on and off,
©2003 Micron Technology, Inc. All rights reserved.
Operations