pnx1700 NXP Semiconductors, pnx1700 Datasheet - Page 231
pnx1700
Manufacturer Part Number
pnx1700
Description
Connected Media Processor
Manufacturer
NXP Semiconductors
Datasheet
1.PNX1700.pdf
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Philips Semiconductors
Volume 1 of 1
PNX17XX_SER_1
Preliminary data sheet
t
t
Figure 6:
H
L
DSACK
: DS_low * pci_clk period shown with DSACK monitoring
: DS_high * pci_clk period shown with DS_high = 1
pci_clk
ADDR
R/WN
DATA
frame
SEL
irdy
trdy
DS
AS
Motorola Write With DSACK
3.1.2 Motorola Style Interface
address
data1
The Motorola style interface supports 8-bit or 16-bit devices. The following timing
diagrams illustrate a 2-byte write and 2-byte read operation. The time between the
falling edge of AS and DS is controlled by the DS time high field in the profile register.
The time low is determined by the DS time low field of the profile register or by the
external device if “wait for ACK” is enabled.
The t
device according to the vendor’s specification. The resolution is a multiple of the PCI
clock period. Refer to the descriptions for the XIO Select Profile registers.
t
H
H
(write time high) and t
t
L
Rev. 1 — 17 March 2006
L
(wait low) timing should be programmed to match the
address + 1
data 2
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Chapter 7: PCI-XIO Module
PNX17xx Series
7-10
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