pnx1700 NXP Semiconductors, pnx1700 Datasheet - Page 363

• Manufacturer Part Number: pnx1700
• Description: Connected Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Volume 1 of 1
PNX17XX_SER_1
Preliminary data sheet
2.3.1 Memory Access Control (DMA CTRL)
2.3 Layer Resources and Functions
The outputs of all mixers are connected to the back-end part of the QVCP --- the
output formatter. The output formatter performs all necessary functions to adopt the
final composited image to the display requirements. Among the functions performed
in the output formatter are: gamma correction, chrominance downsampling, output
formatting, and VBI insertion.
This section focuses on the elements comprising a layer. Note that all of the
described modules are present in each layer exactly once, the justification being that
they (elements) are either always needed for the basic operation of a layer or they are
so small (in design size) that assigning them to the resource pool would be inefficient
due to the multiplexing and routing overhead associated with the pool elements.
QVCP has 4 DMA agents, each of which connects to a 512-Byte buffer in the DMA
adapter. DMA agents 1-2 are hard coded to layer1-2 respectively. DMA4 is used to
fetch a VBI packet or a data packet for DMA-based control-register programming.
DMA3 can be assigned to any of the two layers for supporting the semi-planar input
format.
For video data fetches, the request block size is equal to the initial layer width (before
horizontal scaling). If start_fetch is disabled (i.e., Enable bit 31 of register 0x10E2C8
is programmed to zero), the first DMA request starts right after the layer_enable is
asserted and QVCP works as if prefetch is enabled. However, if start_fetch is enabled
(i.e., Enable bit 31 of register 0x10E2C8 is programmed to one), then the DMA starts
fetching only when QVCP s internal line counter reaches the 12-bit line threshold
programmed in the Fetch Start bits [11:0] of register 0x10E2C8. Data fetched for the
first field (interlaced) or frame (progressive) is not used and is flushed at the FCU
(Flow Control Unit) FIFO. Thereafter, the pixels for the second field/frame start
marching into the FCU FIFO, waiting for the correct layer position. The FCU FIFO
releases pixels only if the x,y coordinates generated by the Screen Timing Generator
(STG) match the layer position. In case of an interlaced output, the field ID is also
checked. The DMA fetch request for the next active video line starts as soon as the
last active pixel of the current line moves from the adapter FIFO into the processing
pipeline and this request must be served in time to guarantee that the first active pixel
of this new line is ready at the FCU FIFO before the STG signals the start of active
video for the new line.
The DMA-based register-control programming only needs to be done once for a
particular display scenario; thus, DMA4 is mainly used for VBI data fetch. QVCP is
designed such that a VBI packet will only be inserted in the horizontal blanking
interval and only one VBI packet is allowed in any one horizontal blanking interval.
To insert this packet, there are two DMA requests. The first request has a block size
of 1 since it is used to fetch only the header (which contains the size information). The
second request is meant to fetch actual data of the required size and so, the
maximum DMA request size (for the second request) is equal the length of horizontal
blanking interval. The VBI data for the current horizontal blanking interval is always
fetched in advance and stored in the DMA buffer (in the adapter). After sending out
this prefetched data, the VBI DMA control unit (DMA4) requests a prefetch of the next
packet (and correct operation requires that the sequence of the next two fetches must
Rev. 1 — 17 March 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX17xx Series
Chapter 11: QVCP
11-6