pnx1700 NXP Semiconductors, pnx1700 Datasheet - Page 817

• Manufacturer Part Number: pnx1700
• Description: Connected Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Volume 1 of 1
Table 8: DCS Network Data Transfer Rules (32 Bits at-a-time Transfer)
Table 9: MTL Memory Bus Byte Address
Table 10: MTL Memory Bus Item DMA Rules
PNX17XX_SER_1
Preliminary data sheet
Module
Item Unit
Size
16 bits
16 bits
32 bits
Data[63:56]
8n+7
Module
Item Unit
Size
8 bits
16 bits
16 bits
32 bits
32 bits
System
Endian Mode
either
big
little
big
little
System
Endian Mode DCS_D[31:24]
big
little
either
Data[55:48]
8n+6
6.4 DMA Across the MTL Bus
The 64-bit MTL bus associates byte-addresses with byte lanes in a fixed manner,
independent of system endian mode, according to
Modules that directly place data in or retrieve data from memory are DMA modules.
High bandwidth modules, or modules that require low latency access to memory,
perform DMA over the MTL Bus.
DMA modules use large (64-byte or larger) block transfers using the 8-byte lanes of
the MTL Bus within the Hub.
Modules that deal with 8, 16 or 32-bit item data sizes and connect directly to the MTL
Bus must follow the rules in
32-bit data items in big-endian modes. Modules that use the DTL interface can rely
on the standard packer and DMA Endian Swap Units to accomplish the MTL Bus
rules.
Data
[63:56]
item # 8
addr a+7
item #4 address a+6
b7...b0 b15...b8
item #4 address a+6
b15...b8 b7...b0
item #2 address a+4 b7...b0 b15...b8 b23...b16
b31...b24
item #2 address a+4 b31...b24 b23...b16
b15...b8 b7...b0
item #1 with address a
bit15.....................................bit0
item #2 with address a+2
bit15.....................................bit0
item (address a) bit31.............................................................................................bit0
Data[47:40]
8n+5
Data
[55:48]
item #7
addr a+6
Data[39:32]
8n+4
Rev. 1 — 17 March 2006
Data
[47:40]
item #6
addr a+5
item #3 address a+4
b7...b0 b15...b8
item #3 address a+4
b15...b8 b...b0
DCS_D[23:16]
Table
Data[31:24]
8n+3
Data
[39:32]
item #5
addr a+4
10. Note in particular the bit numbers of the 16 and
…Continued
Data[23:16]
8n+2
Data
[31:24]
item #4
addr a+3
item #2 address a+2
b7...b0 b15...b8
item #2 address a+2
b15...b8 b7...b0
item #1 address a b7..b0 b15...b8 b23...b16
b31...b24
item #1 address a b31...b24 b23...b16
b15...b8 b7...b0
DCS_D[15:8]
item #2 with address a+2
bit15.....................................bit0
item #1 with address a
bit15.....................................bit0
Table
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Data
[23:16]
item #3
addr a+2
9.
PNX17xx Series
Chapter 29: Endian Mode
Data[15:8]
8n+1
Data
[15:8]
item #2
addr a+1
item #1 address a
b7...b0 b15...b8
item #1 address a
b15...b8 b7...b0
DCS_D[7:0]
Data[7:0]
8n+0
Data
[7:0]
item #1
addr a
29-13