pnx1700 NXP Semiconductors, pnx1700 Datasheet - Page 766

• Manufacturer Part Number: pnx1700
• Description: Connected Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Volume 1 of 1
PNX17XX_SER_1
Preliminary data sheet
Master Transmitter Mode
Serial data is output through SDA while SCL outputs the serial clock. The first byte
transmitted contains the slave address of the receiving device (7-bit SLA) and the
data direction bit as in
‘0’ (W). Serial data is transmitted 8 bits at a time. After each byte is transmitted, an
acknowledge bit is received. START and STOP conditions are output to indicate the
beginning and end of a serial transfer.
In the master transmitter mode, a number of data bytes can be transmitted to the
slave receiver. Before the master transmitter mode can be entered, the
IIC_CONTROL register must be initialized with the EN bit set and the STA and STO
bits reset. EN must be set to enable the IIC module interface. If the AA bit is reset, the
IIC module will not acknowledge its own slave address or the general call address if
they are present on the bus. This will prevent the IIC module interface from entering a
slave mode.
The master transmitter mode may now be entered by setting the STA bit. The IIC
module will then test the I
becomes free. When a START condition is transmitted, the status code in the status
register (STA) will be 0x08. This status code must be used to vector to an interrupt
service routine that loads IIC_DAT with the slave address and the data direction bit
(SLA+W).
When the slave address and direction bit have been transmitted and an
acknowledgment bit has been received, a number of status codes in STA are
possible. The appropriate action to be taken for any of the status codes is detailed in
Table 5 on page
may switch to the master receiver mode by loading IIC_DAT with SLA+R.
Master Receiver Mode
The first byte transmitted contains the slave address of the transmitting device (7-bit
SLA) and the data direction bit. In this case, the data direction bit (R/W) will be logic 1
(R). Serial data is received via SDA while SCL outputs the serial clock. Serial data is
received 8 bits at a time. After each byte is received, an acknowledge bit is
transmitted. START and STOP conditions are output to indicate the beginning and
end of a serial transfer.
In the master receiver mode, a number of data bytes are received from a slave
transmitter. The transfer is initialized as in the master transmitter mode. When the
START condition has been transmitted, the interrupt service routine must load
IIC_DAT with the 7-bit slave address and the data direction bit (SLA+R).
Figure 1:
7
SDA First Transmitted Byte
25-11. After a repeated start condition (state 0x10), the IIC module
Rev. 1 — 17 March 2006
Figure
2
C bus and generate a start condition as soon as the bus
7-Bit SLA
1. In this case the data direction bit (R/W) will be a logic
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX17xx Series
Chapter 25: I
1
2
C Interface
R/W
25-5
0