pnx1700 NXP Semiconductors, pnx1700 Datasheet - Page 241

• Manufacturer Part Number: pnx1700
• Description: Connected Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Volume 1 of 1
PNX17XX_SER_1
Preliminary data sheet
4.3.1 Motorola Interface
4.3.2 NAND-Flash Interface
4.3.3 NOR Flash Interface
4.3 XIO Interface
The first is doing large burst with the memory-read command and the other single or
burst reads. Since the memory read command is intended for relatively short bursts,
only a small amount of data is prefetched. When it is nearly all consumed, additional
data will be prefetched. While the data is being prefetched, the rule the additional
data phases must complete within 8 clocks may come into play. This results in a
disconnect on the first master. When the second master gets the GNT and attempts a
read, it will be RETRIED since the internal state machine is busy with the prefetch of
data requested by the first master. Now the first returns for a continuation of its read.
When data runs low again, additional data will be prefetched, during which another
disconnect occurs. This cycle may repeat until the first master has completed its
entire burst.
The XIO interface uses a part of the PCI interface and some additional signals to
interface with external Flash (NAND and NOR types), NOR-ROM, IDE and Motorola
devices. This function “steals” a PCI cycle and runs an XIO transfer using part of the
PCI bus before giving control back to PCI. The XIO port may be accessed at any time
after the configuration registers have been initialized. Up to five profiles may be
enabled at one time. Each one requires a chip select. When 64 MB addressing is
required, an extra pin (XIO_A[25]) is required with NOR flash and Motorola style
devices. Flash profiles have a dedicated ACK pin to allow PCI transactions to
continue while the device is busy.
In this XIO mode, any 8-bit or 16 bit Motorola 68360 type external slave can be
addressed. For details about connecting a Motorola device to a PCI interface, please
refer to
internal timings are generated in multiples of PCI clock. For programming to do
Motorola cycles, please refer to XIO Sel_X Profile registers. For writes, data-strobe
(DS) assertion time is made programmable by using sel0_we_hi field. There is an
option to use the acknowledge from the device DSACK, or to have a fixed wait time
before probing for read-data and removing DS for write-data.
A flexible interface is provided to interface to a NAND-Flash. There are two registers
that define the type of cycle that will be performed. The read and write strobes can be
programmed independently with a high timer from one to four PCI clocks. A cycle
may contain 0, 1, or 2 commands and 0, 1, 2, 3 or 4 address phases with or without
data. Refer to
to use this interface.
In this XIO mode, any 8-bit or 16-bit NOR flash can be addressed. Up to 64 MB may
be addressed. The DS timing is programmable as is the WN timing. The user has the
option of monitoring the R/BN signal from the flash or using a fixed response for the
DS low timing.
Table
2. Even though the Motorola interface is an asynchronous interface,
Section 3.1.1 NAND-Flash Interface Operation
Rev. 1 — 17 March 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Chapter 7: PCI-XIO Module
PNX17xx Series
for information on how
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