pnx1700 NXP Semiconductors, pnx1700 Datasheet - Page 438

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pnx1700

Manufacturer Part Number
pnx1700
Description
Connected Media Processor
Manufacturer
NXP Semiconductors
Datasheet
Philips Semiconductors
Volume 1 of 1
Table 3: Video Input Formats
PNX17XX_SER_1
Preliminary data sheet
Video Modes
D1
VMI
RAW
HD
8-bit
10-bit
8-bit
10-bit
8-bit
10-bit
8-bit
10-bit
Single Stream (YUV)
Embedded Sync
X
X
signals (as specified in the implementation of the TDA9975(A) decoder from Philips
and the HMP8117 decoder from Intersil). In HD mode HREF, VREF, and FREF are
respectively connected to the VIP module pins hrefhd, vrefhd an frefhd. The
supported mode is shown in
this HD mode, the code is expected to be in the U/V stream; to this end, the current
design checks only one of the streams, the U/V stream, for the presence of the
embedded codes, assuming that any information embedded in the Y stream is
identical (see ITU BT 1120, SMPTE 274M standards). The DUAL_STREAM register
must be programmed to 1 in this mode.
Remark: The explicit sync signals are used only in the HD or DUAL_STREAM mode.
Table 3
input formats, where an X designates the presence (support) of the corresponding
feature.
Figure 6:
tries to capture the above discussion into a quick checklist of implemented
HD Dual Data Stream
Explicit Sync No Sync Embedded Sync
X
Rev. 1 — 17 March 2006
Channel B
Channel A
Figure
X
X
6. Note that for detecting the embedded sync in
FF
FF
EAV/SAV
Identical
00
00
00
00
Dual Stream (Y and U/V)
X
X
XY
XY
U
Y
Chapter 12: Video Input Processor
Y
V
Y
U
Y Y Y
V U V
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX17xx Series
Explicit Sync No Sync
X
X
X
X
12-7

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