pnx1700 NXP Semiconductors, pnx1700 Datasheet - Page 579

• Manufacturer Part Number: pnx1700
• Description: Connected Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Volume 1 of 1
Table 6: SPDIF Input Registers
PNX17XX_SER_1
Preliminary data sheet
Bit
7:0
SPDI_CBITSx Registers
The SPDI_CBITSx registers contain the current block channel status bits. The meaning of each of the channel status fields
can change depending upon whether the input source is a consumer or professional bitstream.
Offset 0x10 A018
31:0
Offset 0x10 A01C
31:0
Offset 0x10 A020
31:0
Offset 0x10 A024
31:0
Offset 0x10 A028
31:0
Offset 0x10 A02C
31:0
SPDI_UBITSx Registers
The SPDI_UBITSx registers contain the current block user data channel bits. The meaning of each of the user data fields is
dependent upon the application.
Offset 0x10 A030
31:0
Symbol
SMASK
CBITS [31:0]
CBITS [31:0]
CBITS [31:0]
CBITS [31:0]
CBITS [31:0]
CBITS [191:159]
UBITS [31:0]
SPDI_CBITS1
SPDI_CBITS2
SPDI_CBITS3
SPDI_CBITS4
SPDI_CBITS5
SPDI_CBITS6
SPDI_UBITS1
…Continued
Acces
s
R/W
R
R
R
R
R
R
R
Value
0x00
0
0
0
0
0
0
0
Rev. 1 — 17 March 2006
Description
Allows per bitmasking the least significant 8 bits of the incoming
samples (corresponding to subframe bits [11:4]). The SMASK
setting only applies to 32-bit capture mode (i.e., SAMP_MODE =
01). The 8 bits of SMASK will determine which subframe bits [11:4]
will be captured and stored in memory.
Note: Setting SMASK[7:0] bits to logic ‘1’ will zero the
corresponding subframe bit [11:4]. Others will pass unchanged.
Channel Status register 1 contains bytes 0, 1, 2 and 3 of the current
Channel Status block according to SPDI_CTL.UCBITS_SEL. It will
always reflect the condition of the current decoded block of 192
frames and will always start at the block boundary. Register bit
meaning will depend upon the source transmission (i.e., consumer
vs. professional). See
Channel Status register 2 contains bytes 4, 5, 6 and 7 of the current
Channel Status block according to SPDI_CTL.UCBITS_SEL.
See
Channel Status register 3 contains bytes 8, 9,10 and 11 of the
current Channel Status block according to
SPDI_CTL.UCBITS_SEL.
Channel Status register 4 contains bytes 12, 13, 14 and 15 of the
current Channel Status block according to
SPDI_CTL.UCBITS_SEL.
Channel Status register 5 contains bytes 16,17,18 and 19 of the
current Channel Status block according to
SPDI_CTL.UCBITS_SEL.
Channel Status register 6 contains bytes 20, 21, 22 and 23 of the
current Channel Status block according to
SPDI_CTL.UCBITS_SEL.
User bit 1 contains the state of user bytes 0,1, 2 and 3 of the block
according to SPDI_CTL.UCBITS_SEL. The SPDI_UBITS register
will always reflect the condition of the current decoded block of 192
frames. Register bit meaning will depend upon the source
transmission.
Table 4
for more details.
Table 3
for more details.
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX17xx Series
Chapter 18: SPDIF Input
18-19