pnx1700 NXP Semiconductors, pnx1700 Datasheet - Page 283

• Manufacturer Part Number: pnx1700
• Description: Connected Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Volume 1 of 1
PNX17XX_SER_1
Preliminary data sheet
valid data and by putting their base addresses in the two BASEx_PTR registers, their
maximum size into the SIZE register and the number of valid words for DMA buffer 1
into the PG_BUF_CTRLx.BUF_LEN bits.
When the FIFO queue is programmed into Pattern Generation mode, i.e.
FIFO_MODE[1]=1, BUF1_RDY and BUF2_RDY flags will get set, indicating that it is
ready for a new DMA buffer containing valid data to be assigned.
Once two valid buffers are assigned and FIFO queue has been enabled the
BUF1_RDY flag must be cleared by software so that the GPIO module can load the
BASE1_PTR and the PG_BUF_CTRLx.BUF_LEN values. After BUF1_RDY has been
cleared the software can program the BUF_LEN value for DMA buffer 2. When the
BUF2_RDY flag is cleared the BASE2_PTR and BUF_LEN values for DMA buffer 2
are loaded by the GPIO modules.
Remark: If the BUF_LEN values for DMA buffer1 and DMA buffer 2 are identical both
BUF1_RDY and BUF2_RDY can be cleared at the same time.
The GPIO hardware now proceeds to empty DMA buffer 1 and transmitting the
samples/timestamps on the selected GPIO pins. Once DMA buffer 1 is empty,
BUF1_RDY is asserted. If BUF2_RDY has been cleared, transmission continues
without interruption from DMA buffer 2. If BUF1_RDY_EN is enabled, a level triggered
system level interrupt request is generated.
While BUF1_RDY is high, the system software is required to assign a new buffer to
BASE1_PTRx, the number of valid words in the new buffer by setting
PG_BUF_CTRLx.BUF_LEN and then clear BUF1_RDY (write a ‘1’ to
BUF1_RDY_CLR) before DMA buffer 2 fills up to avoid an Underrun
condition.Transmission continues from buffer 2, until it is empty. At that time,
BUF2_RDY is asserted, and transmission continues from the new buffer 1, and so on.
If an Underrun condition is reached the GPIO module stops the transmission, holds
current values on the pins and does not warn the CPU that an underrun condition
occurred.
Remark: The BASEx_PTRx and PG_BUF_CTRLx.BUF_LEN values for a DMA
buffer are only loaded into the GPIO pattern generation logic when the relevant
BUFx_RDY signal has been cleared. Since the PG_BUF_CTRLx.BUF_LEN register
is shared between both DMA buffers it important that the value in BUF_LEN when
BUFx_RDY is being cleared is the correct value for that DMA buffer.
The BASEx_PTRx and BUF_LEN values should be stable before software clears
BUFx_RDY.
Remark: The DMA buffer sizes must be a multiple of 64 bytes. SIZE is a static
configuration register and must not be changed during GPIO operation.
Pattern Generation using timestamps
This form of pattern generation is the inverse of event timestamping. Software fills a
(per signal) DMA buffer with timed events (31-bit timestamp + 1-bit direction). The
hardware performs the scheduled event on a selected GPIO pin when the reference
timestamp clock reaches this value.
Rev. 1 — 17 March 2006
Chapter 8: General Purpose Input Output Pins
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX17xx Series
8-12