mc68hc05l25 Freescale Semiconductor, Inc, mc68hc05l25 Datasheet - Page 115

• Manufacturer Part Number: mc68hc05l25
• Description: M68hc05 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

12.8 A/D Status and Control Register
The ADSC register reports the completion of A/D conversion and provides control over oscillator
selection, analog subsystem power, and input channel selection.
CC — Conversion Complete
ADRC — RC Oscillator Control
ADON — A/D Subsystem On
Bits 4:3 — Reserved
CH2:CH0 — Channel Select Bits
Freescale Semiconductor
This read-only status bit is set when a conversion sequence has completed and data is ready to be
read from the ADDR register. CC is cleared when a channel is selected for conversion, when data is
read from the ADDR register, or when the A/D subsystem is turned off. Once a conversion has been
started, conversions of the selected channel will continue every 32 PH2 clock cycles until the ADSC
register is written to again. During continuous conversion operation, the ADDR register will be updated
with new data and the CC bit will be set every 32 PH2 clock cycles. Also, data from the previous
conversion will be overwritten regardless of the state of the CC bit.
When ADRC is set, the A/D subsystem operates from the internal RC oscillator instead of the PH2
clock. The RC oscillator requires a time, t
obtained. See
When the A/D subsystem is turned on (ADON = 1), it requires a time, t
accurate conversion results can be attained.
These bits are not used and always read as zero.
Channel select bits CH2, CH1, and CH0 form a 3-bit field which is used to select an input to the A/D
converter. Channels 0 and 1 correspond to port A input pins PA4 and PA5. Channels 4–6 are used for
reference measurements. In single-chip mode, channels 2, 3, and 7 are reserved. If a conversion is
attempted with channel 2, 3, or 7 selected, the result will be undefined.
selected by bits CH0–CH2.
If the ADON bit is set, and an input from channel 0 or 1 is selected, the corresponding port A pin will
not function as a digital port. If the port A data register is read when DDR = 0 while the A/D is on and
one of the shared input channels is selected using bits CH0–CH2, the corresponding port A pin will
1 = A/D conversion sequence completed
0 = A/D subsystem is off or conversion is in progress
1 = RC OSC on
0 = RC OSC off
1 = A/D subsystem enabled
0 = A/D subsystem disabled
Address:
Reset:
Read:
Write:
12.5.2 Internal versus External Oscillator
$001E
Bit 7
Figure 12-1. A/D Status and Control Register (ADSC)
CC
0
= Unimplemented
ADRC
6
0
MC68HC05L25 Data Sheet, Rev. 3.1
ADON
5
0
RCON,
to stabilize before accurate conversion results can be
4
0
0
for more information.
3
0
0
CH2
2
0
ADON
Table 12-1
A/D Status and Control Register
CH1
1
0
, to stabilize before
lists the inputs
Bit 0
CH0
0
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