mc68hc05l25 Freescale Semiconductor, Inc, mc68hc05l25 Datasheet - Page 49

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mc68hc05l25

Manufacturer Part Number
mc68hc05l25
Description
M68hc05 Microcontrollers Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Chapter 7
Input/Output Ports (I/O)
7.1 Introduction
In single-chip mode, 20 bidirectional input/output (I/O) lines are arranged as three ports: A, B, and C.
Individual bits in these ports are programmable as either inputs or outputs under software control by the
data direction registers (DDRs). If enabled by select bits in RCR or WOMR, port pins may have software
programmable pullup resistors or open-drain outputs, respectively.
7.2 Port A
Port A is an 8-bit bidirectional port which shares bits 0–3 with the key wakeup subsystem, and bit 3 also
is shared with the buzzer subsystem as shown in
Figure 7-1
and
Figure
7-2. Bit 4 is shared with the
analog-to-digital (A/D) converter and the event counter subsystems as shown in
Figure
7-3. Bit 5 is shared
with the A/D converter subsystem as shown in
Figure
7-4. Bit 6 is shared with the time base subsystem
as shown in
Figure
7-5. Each port A pin is controlled by the corresponding bits in a data direction register
and data register enable bits of appropriate subsystems. The port A data register is located at address
$0000. The port A data direction register (DDRA) is located at address $0000 of the option map. Reset
clears the DDRA. The port A data register is unaffected by reset.
Port A bits 0–3, when configured as an output port, is an open-drain output. Each pin can sink a maximum
of 20 mA at V
= 5.0 V and V
(max) = 0.8 V. See
Chapter 15 Electrical
Specifications.
DD
OL
MC68HC05L25 Data Sheet, Rev. 3.1
Freescale Semiconductor
49

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