mc68hc05l25 Freescale Semiconductor, Inc, mc68hc05l25 Datasheet - Page 92

• Manufacturer Part Number: mc68hc05l25
• Description: M68hc05 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Serial Peripheral Interface
10.3.4 Clock Generator
The clock generator includes a 3-bit serial clock counter. The counter starts after detecting the serial clock
and halts after setting SPIF when the counter overflows.
In master mode, this block generates serial clock (SCK) when CPU writes to the data register (SPDR)
and the clock rate is selected by SPR bit in the control register (SPCR).
In slave mode, external clock from the SCK pin is used instead of master mode clock, and SPR has no
effect.
10.3.5 Others
The SPI does not use the data register of port C. Therefore, regardless of whether the SPI is used, the
data register can be read from port C.
10.3.6 Signal Description
The basic signals SDO, SDI, and SCK of SPI are described in the following paragraphs. SCK, SDO, and
SDI pins are shared with port C pins PC0, PC1, and PC2, respectively.
10.3.7 Serial Data Out (SDO)
SDO is an output pin. This pin is shared with port C pin PC1. When the SPI is enabled by SPE bit in the
SPCR, this pin becomes an output pin. When the SPE is cleared, the pin becomes PC1 and thus
becomes an input pin. The state of PC1/SDO can be read any time through PC1 data register.
When the SPI is enabled and PC1/SDO is an output, data output becomes valid at the falling edge of the
serial clock.
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INTERRUPT
0 0 0 0 0 0
SPSR
CLOCK GENERATOR
CONTROLS &
ADDRESS BUS
CONTROL LOGIC
SPCR
Figure 10-1. SPI Block Diagram
0
MC68HC05L25 Data Sheet, Rev. 3.1
HC05 INTERNAL BUS
SPDR
DATA BUS
RESET
D
CK
R
Q
Freescale Semiconductor
SDO
SCK
SDI