mc68hc05l25 Freescale Semiconductor, Inc, mc68hc05l25 Datasheet - Page 75

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mc68hc05l25

Manufacturer Part Number
mc68hc05l25
Description
M68hc05 Microcontrollers Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Chapter 8
Oscillators and Clock
8.1 Introduction
The MC68HC05L25 has dual on-chip oscillators for typical 4.0-MHz and 32.768-kHz crystals. Refer to
Figure
and LCD. Refer to
8.2 OSC Clock Divider and POR Counter
The OSC clock is divided by a 7-bit counter which is used for the system clock, time base, and POR
counter. Clocks divided by 2, 4, and 64 are available for the system clock selections and clock divided by
128 is provided for the time base and POR counter.
The POR counter is a 6-bit clock counter that is driven by the OSC divided by 128. The overflow of this
counter is used for setting FTUP bit, release of power-on reset (POR), and resuming operation from stop
mode.
The 7-bit divider and POR counter are initialized to $0078 by these conditions:
8.3 System Clock Control
The system clock is provided for all internal modules except time base.
Both OSC and XOSC are available as the system clock source. The divide ratio is selected by the SYS1
and SYS0 bits in the MISC register.
By default, OSC divided by two is selected on reset.
Freescale Semiconductor
Power-on detection
When FOSCE bit is cleared
8-1. The clock generated is used by the CPU and by the subsystem modules such as time base
SYS1
0
0
1
1
SYS0
0
1
0
1
Figure
XOSC Divided by 2
OSC Divided by 64
OSC Divided by 2
OSC Divided by 4
8-3.
Divide Ratio
Table 8-1. System Bus Frequency Selection
(Default)
MC68HC05L25 Data Sheet, Rev. 3.1
OSC = 4.0 M
62.5 k
1.0 M
2.0 M
CPU Bus Frequency (Hz)
OSC = 4.1943 M
2.0972 M
1.0486 M
65.536 k
XOSC = 32.768 K
16.384 k
75

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