mc68hc05l25 Freescale Semiconductor, Inc, mc68hc05l25 Datasheet - Page 97

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mc68hc05l25

Manufacturer Part Number
mc68hc05l25
Description
M68hc05 Microcontrollers Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Register Description
10.5.5 Stop/Wait Condition
The following paragraphs describe stop and wait modes.
10.5.6 Stop Mode
The SPI configured as master mode is not operational during stop mode since the system clock and SPI
clock generator are halted. If stop mode occurs while SPI is in progress (transmitting/receiving) and in
master mode, the access will halt and remains halted until stop is released.
Due to the static architecture, the previous conditions of SCK and SDIO are preserved during stop mode.
In slave mode, all accesses are possible during stop mode. However, at the end of transmission, interrupt
occurs but the SPI will not be set immediately until after the system clock starts operating. (This operation
is transparent to the programmer.)
10.5.7 Wait Mode
In wait mode, the CPU halts but will not affect the SPI operation. Therefore, SPI interrupt in master and
slave modes can be executed to wake up the CPU.
MC68HC05L25 Data Sheet, Rev. 3.1
Freescale Semiconductor
97

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