mc68hc05l25 Freescale Semiconductor, Inc, mc68hc05l25 Datasheet - Page 95

• Manufacturer Part Number: mc68hc05l25
• Description: M68hc05 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Bits 3:1 — Reserved
SPR — SPI Clock Rate Select
10.5.2 Serial Peripheral Status Register
SPIF — Serial Transfer Complete Flag
DCOL — Data Collision
Bits 5–0 — Reserved
Freescale Semiconductor
These bits are reserved and always read as zero.
This is the clock rate selection bit. When set, the master mode SCK rate is the system clock divided
by 16. When clear, the rate system clock is divided by two. Reset clears this bit.
SPIF (serial peripheral interface flag) notifies the user that the data transfer between MC68HC05L25
and the external device has been completed. Upon completion of the data transfer, the rising edge of
the eighth serial clock pulse sets SPIF. If SPIE in the SPCR is set, the SPI interrupt (SPII) will be
generated.
While SPIF is set, all access to the SPDR is inhibited until SPSR is read by the CPU. Also, even if the
ninth serial clock is detected, the shift register (SPDR) will not operate.
Clearing the SPIF is accomplished by a software sequence of accessing the SPSR while SPIF is set
and followed by the SPDR access. (SPIF and DCOL can be cleared simultaneously.)
Reset clears this bit.
DCOL (data collision) notifies the user that an invalid access to the SPDR has been made. This bit is
set when an attempt was made to read or write to SPDR while a data transfer was taking place with
an external device. When DCOL is set, access to the SPDR becomes invalid. The transfer continues
uninterrupted without any effect from the SPDR access. This flag does not generate SPI interrupt. It is
read-only.
DCOL is cleared by reading the SPSR with SPIF set followed by a read or write to the SPDR. If the
last part of the clearing sequence is done after another transmission has started, DCOL will be set
again. (DCOL and SPIF can be cleared simultaneously.)
Reset clears this bit.
These bits are unused and always read as zero.
1 = System clock divided by 16
0 = System clock divided by 2
1 = Serial data transfer complete
0 = Serial data transfer in progress
1 = Data collision occurred
0 = Data collision did not occur
Address:
Reset:
Read:
Write:
$000B
SPIF
Bit 7
0
= Unimplemented
Figure 10-3. SPI Status Register (SPSR)
DCOL
6
0
MC68HC05L25 Data Sheet, Rev. 3.1
5
0
0
4
0
0
3
0
0
2
0
0
1
0
0
Register Description
Bit 0
0
0
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