mc68hc05l25 Freescale Semiconductor, Inc, mc68hc05l25 Datasheet - Page 94

• Manufacturer Part Number: mc68hc05l25
• Description: M68hc05 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Serial Peripheral Interface
10.5 Register Description
The SPI has three registers: control register (SPCR), status register (SPSR), and data register (SPDR).
SPCR and SPDR can be read or written by the CPU, but SPSR can only be read.
10.5.1 Serial Peripheral Control Register
SPIE — SPI Interrupt Enable
SPE — SPI Enable
DORD — Data Transmission Order
MSTR — Master Mode Select
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When SPIE (SPI interrupt enable) is set, it allows the occurrence of processor interrupt when SPIF in
the SPSR is set. This interrupt request is accepted when the I bit in the CCR is cleared but inhibited
when I bit is set. If the interrupt request is sent repeatedly while the I bit and only when SPIE and SPIF
are set, the interrupt will occur immediately after the I bit is cleared. Reset clears this bit.
When SPE (SPI enable) is set, it enables the SPI system and connects bit 0 and bit 1 of port C to SCK
and SDIO. Clearing SPE initializes the SPI system and disconnects SPI from port C. Reset clears this
bit.
When DORD is set, the data in the 8-bit shift register (SPDR) is shifted in/out from LSB first. When
clear, the data is shifted MSB first. Reset clears this bit.
This MSTR (master mode select) bit determines whether to output the serial clock internally or input
the clock externally. When set, SPI is in master mode and SCK is configured as an output pin. SCK
outputs the serial clock when CPU writes data to SPDR. When cleared, the SPI is in slave mode and
SCK is configured as an input pin. SCK receives the serial clock externally. Reset clears this bit.
1 = SPI interrupt enabled
0 = SPI interrupt disabled
1 = SPI enabled
0 = SPI disabled
1 = LSB first
0 = MSB first
1 = Master mode
0 = Slave mode
Address:
PC0/SCK should be at V
with an internal or external pullup resistor or by setting DDRC0 = 1 and PC0
= 1 prior to enabling the SPI. Otherwise, the circuit will not initialize
correctly.
Reset:
Read:
Write:
$000A
SPIE
Bit 7
0
Figure 10-2. SPI Control Register (SPCR)
= Unimplemented
SPE
6
0
MC68HC05L25 Data Sheet, Rev. 3.1
DD
DORD
5
0
level before SPI is enabled. This can be done
NOTE
MSTR
4
0
3
0
0
2
0
0
1
0
0
Freescale Semiconductor
Bit 0
SPR
0