mc68hc05l25 Freescale Semiconductor, Inc, mc68hc05l25 Datasheet - Page 41

• Manufacturer Part Number: mc68hc05l25
• Description: M68hc05 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Chapter 6
Interrupts
6.1 Introduction
The MCU can be interrupted in these ways:
6.2 CPU Interrupt Processing
Interrupts cause the processor to save register contents on the stack and to set the interrupt mask (I bit)
to prevent additional interrupts. Unlike reset, hardware interrupts do not cause the current instruction
execution to be halted, but are considered pending until the current instruction is complete.
If interrupts are not masked (I bit in the CCR is clear) and the corresponding interrupt enable bit is set, the
processor will proceed with interrupt processing. Otherwise, the next instruction is fetched and executed.
If an interrupt occurs, the processor completes the current instruction, then stacks the current CPU
register states, sets the I bit to inhibit further interrupts, and finally checks the pending hardware interrupts.
If more than one interrupt is pending after the stacking operation, the interrupt with the highest vector
location shown in
instruction, regardless of the I bit state.
When an interrupt is to be processed, the CPU fetches the address of the appropriate interrupt software
service routine from the vector table at locations $1FF0 through $1FFF as defined in
Freescale Semiconductor
1. Nonmaskable software interrupt instruction (SWI)
2. External interrupt via IRQ (IRQ)
3. Serial peripheral interface interrupt (SPII)
4. Internal time base interrupt (TBI)
5. Key wakeup interrupt (KWI)
6. Event counter overflow interrupt (EVOF)
KWIEN
TBCR2
Regist
INTCR
EVSC
SPSR
N/A
N/A
—
er
R
Table 6-1
Table 6-1. Vector Address for Interrupts and Reset
Name
ECOF
KWIF
IRQF
SPIF
TBIF
Flag
N/A
N/A
—
will be serviced first. The SWI is executed in the same way as any other
MC68HC05L25 Data Sheet, Rev. 3.1
Time Base Periodical
External Interrupt
Serial Peripheral
Event Counter
Key Wakeup
Interrupts
Reserved
Software
Reset
Interrupt
RESET
CPU
SWI
KWI
SPII
IRQ
EVI
TBI
—
$1FFC:$1FFD
$1FFE:$1FFF
$1FFA:$1FFB
$1FF8:$1FF9
$1FF6:$1FF7
$1FF4:$1FF5
$1FF2:$1FF3
$1FF0:$1FF1
Address
Vector
Table
6-1.
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