mc68hc05l25 Freescale Semiconductor, Inc, mc68hc05l25 Datasheet - Page 71

• Manufacturer Part Number: mc68hc05l25
• Description: M68hc05 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

7.5 I/O Port Programming
All bidirectional I/O pins can be programmed as inputs or outputs.
7.5.1 Pin Data Direction
The direction of a pin is determined by the state of its corresponding bit in the associated port data
direction register (DDR). A pin is configured as an output if its corresponding DDR bit is set to a logic 1.
A pin is configured as an input if its corresponding DDR bit is cleared to a logic 0.
The data direction bits DDRA0:DDRA7, DDRB0:DDRB7, and DDRC0:DDRC3 are read/write bits which
can be manipulated with read-modify-write instructions. At power-on or reset, all DDRs are cleared, which
configures all I/O port pins as input (except port B is configured as an LCD port).
7.5.2 Output Pin
When an I/O pin is programmed as an output pin, the state of the corresponding data register bit will
determine the state of the pin. The state of the data register bits can be altered by writing to address $0000
for port A, address $0001 for port B, and address $0002 for port C. Reads of the corresponding data
register bit at address $0000 or $0003 will return the state of the data register bit (not the state of the I/O
pin itself). Therefore, bit manipulation is possible on all pins programmed as outputs.
7.5.3 Input Pin
When an I/O pin is programmed as an input pin, or for an input-only pin, the state of the pin can be
determined by reading the corresponding data register bit. Any writes to the corresponding data register
bit for an input-only pin will be ignored.
If the corresponding bit in the pullup register is set, the input pin will have an activated pullup device. Since
the pullup register bits are read-write, bit manipulation may be used on these register bits.
Freescale Semiconductor
DDR
1. X is don’t care state.
2. Does not affect input, but stored to data register latch
0
0
0
0
1
1
1
1
1
1
Output
Latch
X
X
X
X
0
1
1
0
1
1
INTCR
IRQE
0
0
1
1
0
0
0
1
1
1
WOMR
CWOM
X
X
X
X
X
X
X
X
X
X
Table 7-12. PC3/IRQ I/O Pin Functions
RC Bit
RCR2
MC68HC05L25 Data Sheet, Rev. 3.1
X
X
0
1
0
1
0
1
0
1
Port OUT, OD, Pullup, IRQ
Port OUT, OD, Hi-Z, IRQ
Port OUT, OD, Pullup
Port IN, Pullup, IRQ
Port OUT, OD, Hi-Z
Port OUT, OD, IRQ
Port IN, Hi-Z, IRQ
I/O Pin Modes
Port IN, Pullup
Port OUT, OD
Port IN, Hi-Z
Read/Write
Access to
DDRC3
DDRC3
DDRC3
DDRC3
DDRC3
DDRC3
DDRC3
DDRC3
DDRC3
DDRC3
DDRC3
Access to Data Register
Read
Latch
Latch
Latch
Latch
Latch
Latch
Pin
Pin
Pin
Pin
I/O Port Programming
Latch PC3
Latch, Pin
Latch, Pin
Latch, Pin
Latch, Pin
Latch, Pin
Latch, Pin
Latch
Latch
Latch
Latch
Write
2
2
2
2
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