mc68hc05l25 Freescale Semiconductor, Inc, mc68hc05l25 Datasheet - Page 89

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mc68hc05l25

Manufacturer Part Number
mc68hc05l25
Description
M68hc05 Microcontrollers Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet
9.4 Time Base Control Register 2
TBIF — Time Base Interrupt Flag
TBIE — Time Base Interrupt Enable
TBR1–TBR0 — Time Base Interrupt Rate Select
RTBIF — Reset Time Base Interrupt Flag
Bit 2 — Reserved
COPE — COP Enable
COPC — COP Clear
Freescale Semiconductor
The TBIF bit is set every timeout interval of the time base interrupt. This is a read-only bit and is cleared
by writing a one to the RTBIF bit. Reset clears the TBIF bit. The time base interrupt period between
reset and first TBIF depends on the time elapsed during reset, since the time base divider is not
initialized on reset.
The TBIE bit enables the time base interrupt capability. If TBIF = 1 and TBIE = 1, the time base interrupt
is generated.
The TBR1 and TBR0 bits select one of four rates for the time base interrupt period. The TBI rate is also
related to the COP timeout reset period. See
1 on reset.
The RTBIF bit is a write-only bit and always reads as zero. Writing a one to this bit clears the TBIF bit
and writing zero to this bit has no effect.
This bit is not used and always reads as zero.
When the COPE bit is one, the COP reset function is enabled. This bit is cleared on reset (including
COP timeout reset) and a write to this bit is allowed only once after reset.
Writing a logical 1 to COPC bit clears the 2-bit divider to prevent COP timeout. (The COP timeout
period depends on the TBI rate.) This is a write-only bit and returns to zero when read.
1 = TB interrupt requested when TBIF = 1
0 = TB interrupt disabled
1 = Reset TBIF
0 = No effect
1 = COP enabled
0 = COP disabled
1 = Clear COP timeout divider
0 = No effect
Address:
Reset:
Read:
Write:
$0011
TBIF
Bit 7
0
Figure 9-6. Time Base Control Register 2 (TBCR2)
= Unimplemented
TBIE
6
0
MC68HC05L25 Data Sheet, Rev. 3.1
TBR1
5
0
Table 9-2
TBR0
4
0
and
RTBIF
3
0
0
Table
9-3. These bits are set to a logical
2
0
0
COPE
Time Base Control Register 2
1
0
COPC
Bit 0
0
0
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