mc68hc05l25 Freescale Semiconductor, Inc, mc68hc05l25 Datasheet - Page 96

• Manufacturer Part Number: mc68hc05l25
• Description: M68hc05 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Serial Peripheral Interface
10.5.3 SPI Data Register
The SPDR is used to transmit and receive data on the serial bus.
In master mode, a write to SPDR initiates the transmission/reception of data byte. At transfer completion,
SPIF status bits are set.
In slave mode, a write to the SPDR will not initiate the serial clock. The serial clock is input to the SCK pin
by the external device.
In either master or slave mode, a write to the SPDR is inhibited while this register is shifting (this condition
causes DCOL to set) or when SPIF is set without reading SPSR. In this case, even if an access has
occurred, the access becomes invalid. Refer to SPIF and DCOL descriptions for more information.
When SPI is not being used, SPDR can be used as a data storage. This byte is not affected by reset.
10.5.4 Timing Diagram
Figure 10-5
96
SCK
SDO
DORD = 0
SDI
DORD = 0
SDO
DORD = 1
SDI
DORD = 1
DATA
SAMPLE
illustrates the clock/data timing.
Address:
Reset:
Read:
Write:
$000C
SPD7
Bit 7
Figure 10-4. SPI Data Register (SPDR)
SPD6
MSB
MSB
LSB
LSB
6
Figure 10-5. Clock/Data Timing
MC68HC05L25 Data Sheet, Rev. 3.1
BIT6
BIT6
BIT1
BIT1
SPD5
5
BIT5
BIT5
BIT2
BIT2
Unaffected by Reset
SPD4
4
BIT4
BIT4
BIT3
BIT3
SPD3
BIT3
BIT3
BIT4
BIT4
3
BIT2
BIT2
BIT5
BIT5
SPD2
2
BIT1
BIT1
BIT6
BIT6
SPD1
1
MSB
LSB
LSB
MSB
Freescale Semiconductor
SPD0
Bit 0