tmp88fw45afg TOSHIBA Semiconductor CORPORATION, tmp88fw45afg Datasheet - Page 257
tmp88fw45afg
Manufacturer Part Number
tmp88fw45afg
Description
8 Bit Microcontroller Tlcs-870/x Series
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet
1.TMP88FW45AFG.pdf
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Description of the flash memory erasing mode
1. The 1st through 4th bytes of the transmitted and received data contain the same data as in the flash
2. The 5th byte of the received data contains the command data in the flash memory erasing mode (F0H).
3. When the 5th byte of the received data contains the operation command data shown in Table 21-6, the
4. The 7th thorough m'th bytes of the transmitted and received data contain the same data as in the flash
5. The n’th - 2 byte contains the erasure area specification data. The upper 4 bits and lower 4 bits specify
6. The n’th - 1 byte and n’th byte contain the upper and lower bytes of the checksum, respectively. For
7. After sending the checksum, the device waits for the next operation command data.
memory writing mode.
device echoes back the value which is the same data in the 6th byte position of the received data (in
this case, F0H). If the 5th byte of the received data does not contain the operation command data, the
device enters the halt condition after sending 3 bytes of the operation command error code (63H).
memory writing mode. In the case of a blank product, do not transmit a password string. (Do not transmit
a dummy password string.)
the start address and end address of the erasure area, respectively. For the detailed description, see
"21.13 Specifying the Erasure Area" .
how to calculate the checksum, refer to "21.8 Checksum (SUM)" . Checksum is calculated unless a
receiving error or Intel Hex format error occurs. After sending the end record, the external controller
judges whether the transmission is completed correctly by receiving the checksum sent by the device.
Page 243
TMP88FW45AFG
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