tmp88fw45afg TOSHIBA Semiconductor CORPORATION, tmp88fw45afg Datasheet - Page 86

• Manufacturer Part Number: tmp88fw45afg
• Description: 8 Bit Microcontroller Tlcs-870/x Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

7.2
Watchdog Timer Control
Example :Disabling the watchdog timer
Example :Setting watchdog timer interrupt
7.2.3
7.2.4
Note:If the watchdog timer is disabled during watchdog timer interrupt processing, the watchdog timer interrupt will
in other procedures causes a malfunction of the microcontroller.
by the binary-counter overflow.
master flag (IMF).
is already accepted, the new watchdog timer interrupt is processed immediately and the previous interrupt is held
pending. Therefore, if watchdog timer interrupts are generated continuously without execution of the RETN
instruction, too many levels of nesting may cause a malfunction of the microcontroller.
Watchdog Timer Disable
Watchdog Timer Interrupt (INTWDT)
To disable the watchdog timer, set the register in accordance with the following procedures. Setting the register
When WDTCR1<WDTOUT> is cleared to “0”, a watchdog timer interrupt request (INTWDT) is generated
A watchdog timer interrupt is the non-maskable interrupt which can be accepted regardless of the interrupt
When a watchdog timer interrupt is generated while the other interrupt including a watchdog timer interrupt
To generate a watchdog timer interrupt, set the stack pointer before setting WDTCR1<WDTOUT>.
never be cleared. Therefore, clear the watchdog timer ( set the clear code (4EH) to WDTCR2 ) before disabling
it, or disable the watchdog timer a sufficient time before it overflows.
Note:While the watchdog timer is disabled, the binary counters of the watchdog timer are cleared.
1. Set the interrupt master flag (IMF) to “0”.
2. Set WDTCR2 to the clear code (4EH).
3. Set WDTCR1<WDTEN> to “0”.
4. Set WDTCR2 to the disable code (B1H).
Table 7-1 Watchdog Timer Detection Time (Example: fc = 20 MHz)
DI
LD
LDW
EI
LD
LD
WDTT
00
01
10
11
(WDTCR2), 04EH
(WDTCR1), 0B101H
SP, 010BFH
(WDTCR1), 00001000B
DV1CK = 0
419.430 m
104.858 m
26.214 m
1.678
Watchdog Timer Detection Time[s]
Page 72
NORMAL Mode
: IMF ← 0
: Clears the binary counter
: WDTEN ← 0, WDTCR2 ← Disable code
: IMF ← 1
: Sets the stack pointer
: WDTOUT ← 0
DV1CK = 1
838.861 m
209.715 m
52.429 m
3.355
TMP88FW45AFG