tmp88fw45afg TOSHIBA Semiconductor CORPORATION, tmp88fw45afg Datasheet - Page 66

• Manufacturer Part Number: tmp88fw45afg
• Description: 8 Bit Microcontroller Tlcs-870/x Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

5.5
Port P4 (P47 to P40)
5.5
Table 5-4
Note 1: i = 7 to 0
Note 2: OFDRST shows a reset signal of oscillation frequency detection.
This port is switched between input and output modes using the P4 port input/output control register (P4CR). When
reset, the P4CR register is initialized to 0, with the P4 port set for input mode. Also, the output latch (P4DR) is initialized
to 0 when reset.
is used to select open-drain or tri-state mode for the port. When reset, the P4ODE register is initialized to 0, with tri-
state mode selected for the port.
the oscillation frequency detection reset and Port P4 becomes high impedance.
Port P4 (P47 to P40)
Port P4 is an 8-bit input/output port shared with serial interface input/output and serial PROM mode control input.
The P4 port contains bit wise programmable open-drain control. The P4 port open-drain control register (P4ODE)
If high frequency oscillation stops or becomes abnormal in NORMAL/IDLE mode, the TMP88FW45AFG generates
P4ODE
0
0
0
0
1
1
1
1
P4CR
Control output
0
0
1
1
0
0
1
1
Control input
Data output
Data input
OFDRST
P4ODEi
OUTEN
P4CRi
STOP
P4DR
0
1
0
1
0
1
0
1
Output latch
D
Data input (by reading instruction)
Input Data from port (Low)
Input Data from port (Low)
Figure 5-6 Port P4
Q
"0" (output latch data)
"1" (output latch data)
Input Data from port
Input Data from port
Input Data from port
Input Data from port
Page 52
Input Data from port (Low)
Input Data from port (Low)
"0" (output latch data)
"1" (output latch data)
Input Data from port
Input Data from port
Input Data from port
Input Data from port
Control input
P4i
TMP88FW45AFG
Output data
Hi-Z
Hi-Z
Hi-Z
Hi-Z
"0"
"1"
"0"
"0"