tmp88fw45afg TOSHIBA Semiconductor CORPORATION, tmp88fw45afg Datasheet - Page 45

• Manufacturer Part Number: tmp88fw45afg
• Description: 8 Bit Microcontroller Tlcs-870/x Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Example :Register bank switching
3.3.2
3.3.2.1
3.3.2.2
PINTxx:
VINTxx:
level of current servicing interrupt is requested.
acceptable interrupt sources are selectively enabled by the individual interrupt enable flags. But don’t use the
read-modify-write instruction for EIRL(0003AH) on the pseudo non-maskable interrupt service task.
before setting IMF to “1”. As for non-maskable interrupt, keep interrupt service shorten compared with length
between interrupt requests; otherwise the status cannot be recovered as non-maskable interrupt would simply
nested.
IMF) are automatically saved on the stack, but the accumulator and others are not. These registers are saved by
software if necessary. When multiple interrupt services are nested, it is also necessary to avoid using the same
data memory area for saving registers. The following four methods are used to save/restore the general-purpose
registers.
Saving/restoring general-purpose registers
A maskable interrupt is not accepted until the IMF is set to “1” even if the maskable interrupt higher than the
In order to utilize nested interrupt service, the IMF is set to “1” in the interrupt service program. In this case,
To avoid overloaded nesting, clear the individual interrupt enable flag whose interrupt is currently serviced,
During interrupt acceptance processing, the program counter (PC) and the program status word (PSW, includes
interrupt service task. To make up its data memory efficiency, the common bank is assigned for non-multiple
interrupt factor.
current interrupt register bank automatically. Thus, no need to restore the RBS by a program.
the bank register "0" is assigned for main task and the bank register "1 to 15" are for the each interrupt service
task.
By switching to non-use register bank, it can restore the general-purpose register at high speed.
Usually the bank register "0" is assigned for main task and the bank register "1 to 15" are for the each
It can return back to main-flow by executing the interrupt return instructions ([RETI]/[RETN]) from the
By switching to non-use register bank, it can restore the general-purpose register at high speed. Usually
Using Automatic register bank switching
Using register bank switching
FFFE4H
FFFE5H
FFFE6H
FFFE7H
(interrupt processing)
RETI
:
DP
DB
Vector table address
Figure 3-2 Vector table address, Entry address
45H
23H
01H
06H
PINTxx
1
Vector
RBS
control code
Page 31
12345H
12346H
12347H
12348H
Entry address
; Begin of interrupt routine
; End of interrupt
; PINTxx vector address setting
; RBS <- RBS + 1 RBS setting on PINTxx
Interrupt
service
program
TMP88FW45AFG