tmp88fw45afg TOSHIBA Semiconductor CORPORATION, tmp88fw45afg Datasheet - Page 7
tmp88fw45afg
Manufacturer Part Number
tmp88fw45afg
Description
8 Bit Microcontroller Tlcs-870/x Series
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet
1.TMP88FW45AFG.pdf
(294 pages)
- Current page: 7 of 294
- Download datasheet (4Mb)
2. Functional Description
3. Interrupt Control Circuit
Difference between TMP88FW45FG and TMP88FW45AFG
TMP88FW45AFG
1.1 Features......................................................................................................................................1
1.2 Pin Assignment..........................................................................................................................3
1.3 Block Diagram...........................................................................................................................4
1.4 Pin Names and Functions..........................................................................................................5
2.1 Functions of the CPU Core........................................................................................................9
3.1 Interrupt latches (IL39 to IL2) ................................................................................................26
3.2 Interrupt enable register (EIR) ................................................................................................27
3.3
3.4 Software Interrupt (INTSW) ...................................................................................................34
3.5 External Interrupts ..................................................................................................................35
2.1.1
2.1.2
2.1.3
2.1.4
2.1.5
3.2.1
3.2.2
3.3.1
3.3.2
3.3.3
3.4.1
3.4.2
2.1.4.1
2.1.4.2
2.1.4.3
2.1.4.4
2.1.5.1
2.1.5.2
2.1.5.3
2.1.5.4
2.1.5.5
3.3.2.1
3.3.2.2
3.3.2.3
3.3.2.4
Interrupt Sequence .................................................................................................................30
Memory Address Map.........................................................................................................................................................9
Program Memory (ROM)..................................................................................................................................................10
Data Memory (RAM)........................................................................................................................................................10
System Clock Control Circuit............................................................................................................................................11
Reset Circuit......................................................................................................................................................................23
Interrupt master enable flag (IMF) ...................................................................................................................................27
Individual interrupt enable flags (EF39 to EF3) ...............................................................................................................27
Interrupt acceptance processing is packaged as follows. ..................................................................................................30
Saving/restoring general-purpose registers .......................................................................................................................31
Interrupt return ..................................................................................................................................................................33
Address error detection .....................................................................................................................................................34
Debugging .........................................................................................................................................................................34
Clock Generator
Timing Generator
Standby Control Circuit
Controlling Operation Modes
External Reset Input
Address Trap Reset
Watchdog Timer Reset
System Clock Reset
Oscillation Frequency Detection Reset
Using Automatic register bank switching
Using register bank switching
Using PUSH and POP instructions
Using data transfer instructions
Table of Contents
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