se97b NXP Semiconductors, se97b Datasheet - Page 12

• Manufacturer Part Number: se97b
• Description: Ddr Memory Module Temp Sensor With Integrated Spd
• Manufacturer: NXP Semiconductors

NXP Semiconductors
SE97B_1
Product data sheet
7.7 SMBus TIMEOUT
7.8 SMBus Alert Response Address (ARA)
Table 5
registers.
Table 5.
The SE97B supports SMBus TIMEOUT feature. If the host holds SCL LOW more than
35 ms, the SE97B would reset its internal state machine to the bus IDLE state to prevent a
system bus hang-up. This feature is turned on by default and release SDA. The SMBus
TIMEOUT can be disabled by writing a ‘1’ to SMBUS[7].
Remark: When SMBus TIMEOUT is enabled, the I
by the SMBus TIMEOUT specification limit of 10 kHz.
The SE97B has no SCL driver, so it cannot hold the SCL line LOW.
The SE97B supports SMBus ALERT when it is programmed for the Interrupt mode and
when the EVENT polarity bit is set to ‘0’. In Comparator mode or when the EVENT polarity
bit is set to ‘1’, the SMBus ALERT address is not acknowledged. The EVENT pin can be
ANDed with other EVENT or interrupt signals from other slave devices to signal their
intention to communicate with the host controller. When the host detects EVENT or other
interrupt signal LOW, it issues an ARA to which a slave device would respond with its
address. When there are multiple slave devices generating an ALERT the SE97B
performs bus arbitration with the other slaves. If it wins the bus, it responds to the ARA
and then clears the EVENT pin. This feature is turned off by default and can be enabled
by writing a ‘0’ to SMBUS[0].
Remark: Either in comparator mode or when the SE97B crosses the critical temperature,
the host must also read the EVENT status bit and provide remedy to the situation by
bringing the temperature to within the alarm window or below the critical temperature if
that bit is set. Otherwise, the EVENT pin will not get de-asserted.
Register
01h
02h
03h
04h
22h
shows the default values and the example value to be programmed to these
Registers to be initialized
Default value
0000h
0000h
0000h
0000h
21h
Rev. 01 — 27 January 2010
Example value
0209h
0550h
1F40h
05F0h
21h
DDR memory module temp sensor with integrated SPD
Description
Configuration register
Upper Boundary Alarm Trip register = 85 °C
Lower Boundary Alarm Trip register = −20 °C
Critical Alarm Trip register = 95 °C
SMBus register = no change
•
•
•
hysteresis = 1.5 °C
EVENT output = Interrupt mode
EVENT output is enabled
2
C-bus minimum bus speed is limited
© NXP B.V. 2010. All rights reserved.
SE97B
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