se97b NXP Semiconductors, se97b Datasheet - Page 13

• Manufacturer Part Number: se97b
• Description: Ddr Memory Module Temp Sensor With Integrated Spd
• Manufacturer: NXP Semiconductors

NXP Semiconductors
SE97B_1
Product data sheet
Fig 5.
Fig 6.
SDA
SCL
START
S
A = ACK = Acknowledge bit. W = Write bit = 0. R = Read bit = 1.
SMBus/I
How SE97B responds to SMBus Alert Response Address
SMBus ALERT
host detects
A6
1
7.9 SMBus/I
2
A5
C-bus write to the Pointer register
2
START bit
device address and write
The data registers in this device are selected by the Pointer Register. At power-up, the
Pointer Register is set to ‘00h’, the location for the Capability Register. The Pointer
Register latches the last location to which it was set. Each data register falls into one of
three types of user accessibility:
A ‘write’ to this device will always include the address byte and the pointer byte. A write to
any register other than the Pointer register requires two data bytes.
Reading this device can take place either of two ways:
The data byte has the most significant bit first. At the end of a read, this device can accept
either Acknowledge (ACK) or No Acknowledge (NACK) from the Master (No Acknowledge
is typically used as a signal for the slave that the Master has read its last byte). It takes
this device 125 ms to measure the temperature. Refer to timing diagrams
Figure 9
S
A4
3
•
•
•
•
•
Read only
Write only
Write/Read same address
If the location latched in the Pointer register is correct (most of the time it is expected
that the Pointer register will point to one of the Temperature register (as it will be the
data most frequently read), then the read can simply consist of an address byte,
followed by retrieving the two data bytes.
If the Pointer register needs to be set, then an address byte, pointer byte,
repeat START, and another address byte will accomplish a read.
0
A3
4
0
master sends a START bit,
ARA and a read command
for how to program the device.
Alert Response Address
2
A2
5
C-bus interface
0
1
A1
6
1
A0
7
Rev. 01 — 27 January 2010
0
W
8
0
read
by device
DDR memory module temp sensor with integrated SPD
ACK
1
A
9
acknowledge
0
D7
1
0
The last bit of slave address
D6
2
Slave acknowledges and
sends its slave address.
0
is hard coded '0'.
D5
1
3
device address
register address
1
D4
4
A2
D3
5
A1
no acknowledge
A0
D2
6
0
sends a STOP bit
host NACK and
D1
7
1
© NXP B.V. 2010. All rights reserved.
002aac685
D0
8
STOP bit
P
Figure 6
by device
SE97B
ACK
A
9
002aab308
STOP
to
13 of 53
P