se97b NXP Semiconductors, se97b Datasheet - Page 24

• Manufacturer Part Number: se97b
• Description: Ddr Memory Module Temp Sensor With Integrated Spd
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 12.
SE97B_1
Product data sheet
Bit
Symbol
Default
Access
Bit
Symbol
Default
Access
CONFIG - Configuration register (address 01h) bit allocation
CTLB
8.3 CONFIG — Configuration register (01h, 16-bit read/write)
R/W
15
R
0
7
0
Table 13.
Bit
15:11
10:9
AWLB
R/W
14
R
0
6
0
Symbol
RFU
HEN
Configuration register (address 01h) bit description
CEVNT
RFU
13
Description
reserved for future use; must be ‘0’.
Hysteresis Enable.
When enabled, hysteresis is applied to temperature movement around
trigger points. For example, consider the behavior of the ‘Above Alarm
Window’ bit (bit 14 of the Temperature register) when the hysteresis is set to
3 °C. As the temperature rises, bit 14 will be set to ‘1’ (temperature is above
the alarm window) when the Temperature register contains a value that is
greater than the value in the Alarm Temperature Upper Boundary Register. If
the temperature decreases, bit 14 will remain set until the measured
temperature is less than or equal to the value in the Alarm Temperature
Upper Boundary register minus 3 °C. (Refer to
Similarly, the ‘Below Alarm Window’ bit (bit 13 of the Temperature register)
will be set to ‘0’ (temperature is equal to or above the Alarm Window Lower
Boundary Trip register) when the value in the Temperature register is equal
to or greater than the value in the Alarm Temperature Lower Boundary
register. As the temperature decreases, bit 13 will be set to ‘1’ when the
value in the Temperature register is equal to or less than the value in the
Alarm Temperature Lower Boundary register minus 3 °C. Note that
hysteresis is also applied to EVENT pin functionality.
When either of the Critical Trip or Alarm Window lock bits is set, these bits
cannot be altered until unlocked.
R
W
0
5
0
00 — disable hysteresis (default)
01 — enable hysteresis at 1.5 °C
10 — enable hysteresis at 3 °C
11 — enable hysteresis at 6 °C
Rev. 01 — 27 January 2010
DDR memory module temp sensor with integrated SPD
ESTAT
12
R
0
R
4
0
EOCTL
R/W
11
R
0
3
0
R/W
CVO
R/W
10
0
2
0
Figure 4
HEN
R/W
R/W
EP
9
0
and
1
0
© NXP B.V. 2010. All rights reserved.
Table
SE97B
14).
SHMD
EMD
R/W
R/W
8
0
0
0
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