k4j55323qg Samsung Semiconductor, Inc., k4j55323qg Datasheet - Page 11

• Manufacturer Part Number: k4j55323qg
• Description: 256mbit Gddr3 Sdram
• Manufacturer: Samsung Semiconductor, Inc.

CAS LATENCY (READ LATENCY)
data. The latency can be set to 4~15 clocks. If a READ command is registered at clock edge n, and the latency is m clocks, the data will
be available nominally coincident with clock edge n+m. Below table indicates the operating frequencies at which each CAS latency set-
ting can be used. Reserved states should not be used as unknown operation or incompatibility with future versions may result.
K4J55323QG
COMMAND
COMMAND
The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output
RDQS
RDQS
/CK
CK
/CK
CK
DQ
DQ
SPEED
-16
-20
-10
-12
-14
-11
Burst Length = 4 in the cases shown
Shown with nominal t
CL=15
-
-
READ
READ
T0
T0
CL=14
AC
TBD
TBD
and nominal t
CL=13
DON’T CARE
-
-
NOP
NOP
T6
T5
Allowable operating frequency (MHz)
DSDQ
CL=12
CAS Latency
- 11 /53 -
CL = 8
CL = 7
TRANSITIONING DATA
CL=11
≤ 800
NOP
NOP
T7
T6
CL=10
≤ 700
-
≤
CL=9
256M GDDR3 SDRAM
600
-
-
NOP
NOP
T8
T7
Rev. 1.3 June 2006
CL=8
-
-
-
-
T8n
T7n
≤
CL=7
500
-
-
-