k4j55323qg Samsung Semiconductor, Inc., k4j55323qg Datasheet - Page 15

• Manufacturer Part Number: k4j55323qg
• Description: 256mbit Gddr3 Sdram
• Manufacturer: Samsung Semiconductor, Inc.

DLL ENABLE/DISABLE
ation after disabling the DLL for debugging or evaluation. (When the device exits self refresh mode, the DLL is enabled automatically.)
Any time the DLL is enabled, 20K clock cycles must occur before an any command can be issued.
DATA TERMINATION
and 120
DATA DRIVER IMPEDANCE
driver impedance is set to RQ/6 and it’s tolerance is determined by the calibration accuracy of the device. When any other value is
selected the target impedance is set nominally to the desired impedance. However, the accuracy is now determined by the device’s spe-
cific process corner, applied voltage and operating temperature.
ADDITIVE LATENCY
clock cycles that is to be added to CL after CAS is captured by the rising edge of CK. Thus the total CAS latency is determined by add-
ing CL and AL.
K4J55323QG
The DLL must be enabled for normal operation. DLL enable is required during power-up initialization and upon returning to normal oper-
The Data Termination, DT, is used to determine the value of the internal data termination resisters. The GDDR3 SDRAM supports 60
The Data Driver impedance (DZ) is used to determine the value of the data drivers impedance. When auto calibration is used the data
The Additive Latency function (AL) is used to optimize the command bus efficiency. The AL value is used to determine the number of
Ω
termination. The termination may also be disabled for testing and other purposes.
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256M GDDR3 SDRAM
Rev. 1.3 June 2006
Ω