k4j55323qg Samsung Semiconductor, Inc., k4j55323qg Datasheet - Page 14

• Manufacturer Part Number: k4j55323qg
• Description: 256mbit Gddr3 Sdram
• Manufacturer: Samsung Semiconductor, Inc.

* ZQ : Resistor connection pin for On-die termination
* 1 : ALL ODT will be disabled
RFU(Reserved for future use) should stay "0" during EMRS cycle
ten by asserting low on CS, RAS, CAS, WE and high on BA0(The GDDR3 SDRAM should be in all bank precharge with CKE already
high prior to writing into the extended mode register). The state of address pins A0 ~ A11 and BA0,BA1 in the same cycle as CS, RAS,
CAS and WE going low are written in the extended mode register. The minimum clock cycles specified as tMRD are required to com-
plete the write operation in the extended mode register. 4 kinds of the output driver strength are supported by EMRS (A1, A0) code. The
mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks
are in the idle state. "High" on BA0 is used for EMRS. Refer to the table for specific codes.
ADDR/CMD Termination
Default value is determined by CKE status at
the rising edge of RESET during power-up
K4J55323QG
7.4 EXTENDED MODE REGISTER SET(EMRS)
The extended mode register stores the data output driver strength and on-die termination options. The extended mode register is writ-
BA
0
0
A
0
1
11
1
BA
0
BA
0
1
1
Half of default
Termination
0
Default
EMRS
BA
A
MRS
1
n
0
~ A
0
Term
A
11
Vendor ID
A
0
1
10
Ron of Pull-up
A
ID
10
Vendor ID
0
1
A
9
Off
On
RON
RON
A
40
60
9
Ω
Ω
A
0
8
tWR
tWR
A
- 14 /53 -
0
0
0
0
1
1
1
1
A
7
7
0
0
1
1
0
0
1
1
DLL
A
5
DLL
A
A
0
1
6
6
0
1
0
1
0
1
0
1
A
4
Disable
Enable
DLL
A
5
tWR
tWR
11
13
10
5
6
7
8
9
A
4
256M GDDR3 SDRAM
A
Termination
Data
3
A
0
0
1
1
3
Rev. 1.3 June 2006
Drive Strength
Termination
A
0
0
1
1
A
0
1
0
1
A
2
1
2
0
1
0
1
ODT Disabled
A
Termination
0
Drive Strength
Reserved
A
1
Drive Strength
ZQ/4
ZQ/2
Autocal
30
40
50
Ω
Ω
Ω
A
*1
0