k4j55323qg Samsung Semiconductor, Inc., k4j55323qg Datasheet - Page 23

• Manufacturer Part Number: k4j55323qg
• Description: 256mbit Gddr3 Sdram
• Manufacturer: Samsung Semiconductor, Inc.

7.9.1 BANK/ROW ACTIVATION
K4J55323QG
7.9 OPERATIONS
row in that bank must be “opened.” This is accomplished via the ACTIVE command, which selects
both the bank and the row to be activated.
that row, subject to the t
rounded up to the next whole number to determine the earliest clock edge after the ACTIVE com-
mand in which a READ or WRITE command can be entered. For example, a t
16ns with a 800MHz clock (1.25ns period) results in 12.8 clocks rounded to 13. This is reflected in
below figure, which covers any case where 12<t
previous active row has been “closed”(precharged). The minimum time interval between successive
ACTIVE commands to the same bank is defined by t
accessed, which results in a reduction of total row access overhead. The minimum time interval
between successive ACTIVE commands to different banks is defined by t
** Any system or application incorporating random access memory products should be
properly designed, tested and qualified to ensure proper use or access of such memory
products. Disproportionate, excessive and/or repeated access to a particular address or
addresses may result in reduction of product life.
Before any READ or WRITE commands can be issued to a banks within the GDDR3 SDRAM, a
After a row is opened with an ACTIVE command, a READ or WRITE command may be issued to
The same procedure is used to convert other specification limits from time units to clock cycles).
A subsequent ACTIVE command to a different row in the same bank can only be issued after the
A subsequent ACTIVE command to another bank can be issued while the first bank is being
Example : Meeting t
COMMAND
BA0,BA1
A0-A11
/CK
CK
Bank x
ACT
Row
RCD
T0
specification. t
RCD
NOP
T1
RCD(min)
t
RRD
RCD(min)
NOP
should be divided by the clock period and
T2
RC
.
/t
CK
≤
13.
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Bank y
ACT
Row
t
T3
RCD
RRD
.
RCD
NOP
T4
specification of
NOP
T12
256M GDDR3 SDRAM
BA0,BA1
A0-A11
Activating a Specific Row
Rev. 1.3 June 2006
RD/WR
Bank y
/CAS
/RAS
CKE
Col
T13
/CK
/WE
CK
/CS
in a Specific Bank
BA = Bank Address
RA = Row Address
HIGH
DON’T CARE
RA
BA
NOP
T14