k4j55323qg Samsung Semiconductor, Inc., k4j55323qg Datasheet - Page 12

• Manufacturer Part Number: k4j55323qg
• Description: 256mbit Gddr3 Sdram
• Manufacturer: Samsung Semiconductor, Inc.

WRITE LATENCY
input data. The latency can be set from 1 to 7 clocks depending in the operating frequency and desired current draw. When the write
latencies are set to 1 or 2 or 3 clocks, the input receivers never turn off when the WRITE command is registered. If a WRITE command
is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident with clock edge n+m. Reserved
states should not be used as unknown operation or incompatibility with future versions may result.
K4J55323QG
The Write latency (WL) is the delay, in clock cycles, between the registration of a WRITE command and the availability of the first bit of
COMMAND
COMMAND
WDQS
/CK
CK
/CK
CK
WDQS
DQ
DQ
Burst Length = 4 in the cases shown
WRITE
WRITE
T0
T0
DON’T CARE
NOP
NOP
T2
T1
WL = 4
WL = 3
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TRANSITIONING DATA
NOP
NOP
T3
T2
256M GDDR3 SDRAM
NOP
NOP
T4
T3
Rev. 1.3 June 2006
T4n
T3n