k4j55323qg Samsung Semiconductor, Inc., k4j55323qg Datasheet - Page 43

• Manufacturer Part Number: k4j55323qg
• Description: 256mbit Gddr3 Sdram
• Manufacturer: Samsung Semiconductor, Inc.

TRUTH TABLE - CURRENT STATE BANK n
Note :
5. The following states must not be interrupted by any executable command ; COMMAND INHIBIT or NOP commands must be applied on each positive
clock edge during these states.
10. READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto
11. Requires appropriate DM masking.
12. A WRITE command may be applied after the completion of the READ burst.
K4J55323QG
1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see TRUTH TABLE- CKE ) and after t
2. This table describes alternate bank operation, except where noted (i.e., the current state is for bank n and the commands shown are those allowed
6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks are idle, and bursts are not in progress.
8. May or may not be bank-specific ; If multiple banks are to be precharged, each must be in a valid state for precharging.
9. Left blank
CURRENT STATE
Precharge Enabled
Precharge Enabled
self refresh).
to be issued to bank m, assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in the notes below.
(Auto-Precharge
(Auto-Precharge
Auto-Precharge)
Auto-Precharge)
Row Activating,
precharge disabled.
READ or WRITE : Starts with registration of the ACTIVE command and ends the last valid data nibble.
Prechrging
Disabled)
Active, or
Disable)
Read w/ Auto- : Starts with registration of an READ command with auto precharge enabled and ends
Write w/ Auto- : Starts with registration of a WRITE command with auto precharge enabled and ends
Precharge All : Starts with registration of a PRECHARGE ALL command and ends when t
Read
Write
Read
(With
Write
(With
Any
Idle
Refreshing : Starts with registration of an AUTO REFRESH command and ends when t
Register has been met. Once t
Accessing Mode : Starts with registration of a LOAD MODE REGISTER command and ends when t
when tRP has been met. Once t
when t
Once t
Once t
/CS
H
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
RP
RP
RC
has been met. Once t
/RAS /CAS
is met, all banks will be in the idle state.
is met, the GDDR3(x32) will be in the all banks idle state.
X
H
H
X
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
MRD
X
H
X
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
is met, the GDDR3(x32) SDRAM will be in the all banks idle state.
/WE
H
H
H
H
H
H
H
H
H
H
H
H
X
X
L
L
L
L
L
L
L
L
L
L
RP
RP
is met, the bank will be in the idle state.
DESELECT (NOP/ continue previous operation)
NO OPERATION (NOP/continue previous operation)
DATA TERMINATOR DISABLE
Any Command Otherwise Allowed to Bank m
ACTIVE (Select and activate row)
READ (Select column and start READ burst)
WRITE (Select Column and start WRITE burst)
PRECHARGE
ACTIVE (Select and activate row)
READ (Select column and start new READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE
ACTIVE (Select and activate row)
READ (Select column and start READ burst)
WRITE (Select column and start new WRITE burst)
PRECHARGE
ACTIVE (Select and activate row)
READ (Select column and start new READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE
ACTIVE (Select and activate row)
READ (Select column and start READ burst)
WRITE (Select column and start new WRITE burst)
PRECHARGE
is met, the bank will be in the idle state.
- COMMAND TO BANK m
- 43 /53 -
COMMAND/ ACTION
RP
RC
is met.
is met.
XSNR
256M GDDR3 SDRAM
has been met (if the previous state was
MRD
Rev. 1.3 June 2006
NOTES
6, 7
6
6
6
6
6
6
6
6
6