k4j55323qg Samsung Semiconductor, Inc., k4j55323qg Datasheet - Page 9

• Manufacturer Part Number: k4j55323qg
• Description: 256mbit Gddr3 Sdram
• Manufacturer: Samsung Semiconductor, Inc.

Write Latency
7.3 MODE REGISTER SET(MRS)
K4J55323QG
ing mode, test mode and various vendor specific options to make GDDR3 SDRAM useful for variety of different applications. The
default value of the mode register is not defined, therefore the mode register must be written after EMRS setting for the proper opera-
tion. The mode register is written by asserting low on CS, RAS, CAS and WE (The GDDR3 SDRAM should be in active mode with CKE
already high prior to writing into the mode register). The state of address pins A
CAS and WE going low is written in the mode register. Minimum clock cycles specified as tMRD are required to complete the write oper-
ation in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during
operation as long as all banks are in the idle state. The mode register is divided into various fields depending on functionality. The Burst
length uses A
reset. A
RFU(Reserved for future use) should
stay "0" during MRS cycle
A
BA
The mode register stores the data for controlling the various operating modes of GDDR3 SDRAM. It programs CAS latency, address-
0
0
0
0
1
1
1
1
0
0
11
BA
1
0
9
1
A
0
0
1
1
0
0
1
1
BA
~ A
0
1
10
0
11
0
BA
are used for Write latency. Refer to the table for specific codes for various addressing modes and CAS latencies.
A
~ A
0
0
1
0
1
0
1
0
1
EMRS
A
0
MRS
9
n
1
. CAS latency (read latency from column address) uses A
~ A
Write Latency
A
0
Reserved
11
1
2
3
4
5
6
7
A
WL
10
A
Note : DLL reset is self-clearing
DLL
9
0
1
A
8
DLL Reset
DLL
A
8
Yes
No
Test Mode
CAS Latency
0
1
A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A
7
TM
2
A
7
Normal
- 9 /53 -
mode
0
0
0
0
A
0
0
0
0
1
1
1
1
1
1
1
1
Test
6
A
A
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
6
5
CAS Latency
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
A
4
2
A
, A
5
0
Reserved(12)
Reserved(13)
Reserved(14)
Reserved(15)
CAS Latency
6
~ A
Reserved
Reserved
Reserved
Reserved
~ A
11
10
11
8
9
4
5
6
7
4
A
. A
and BA
Burst Type
4
A
0
1
7
3
is used for test mode. A
256M GDDR3 SDRAM
A
BT
0
Burst Type
, BA
3
Sequential
Reserved
Burst Length
1
in the same cycle as CS, RAS,
Rev. 1.3 June 2006
A
0
0
1
1
A
CL
1
2
A
0
1
0
1
0
Burst Length
A
1
8
Burst Length
is used for DLL
Reserved
Reserved
A
4
8
0