k4j55323qg Samsung Semiconductor, Inc., k4j55323qg Datasheet - Page 49

• Manufacturer Part Number: k4j55323qg
• Description: 256mbit Gddr3 Sdram
• Manufacturer: Samsung Semiconductor, Inc.

10.3 CLOCK INPUT OPERATING CONDITIONS
Recommended operating conditions (
Note :
1. This provides a minimum of 1.16V to a maximum of 1.36V, and is always 70% of VDDQ
2. For AC operations, all DC clock requirements must be satisfied as well.
3. The value of VIX is expected to equal 70% VDDQ for the transmitting device and must track variations in the DC level of the same.
4. VID is the magnitude of the difference between the input level in CK and the input level on /CK.
5. The CK and /CK input reference level (for timing referenced to CK and /CK) is the point at which CK and /CK cross; the input reference level for signals
6. CK and /CK input slew rate must be > 3V/ns
K4J55323QG
Clock Input Mid-Point Voltage ; CK and /CK
Clock Input Voltage Level; CK and /CK
Clock Input Differential Voltage ; CK and /CK
Clock Input Differential Voltage ; CK and /CK
Clock Input Crossing Point Voltage ; CK and /CK
Note : 1 . Outputs measured into equivalent load of 10pf at a driver impedance of 40
other than CK and /CK is VREF.
Parameter/ Condition
GDDR3
0°C ≤ Tc ≤85°C ; VDD=1.8V + 0.1V, VDDQ=1.8V + 0.1V
V
REF
ZQ
Output Load Circuit
240
Symbol
V
V
V
V
V
MP(DC)
IN(DC)
ID(DC)
ID(AC)
IX(AC)
Ω
1.26V
- 49 /53 -
Z
0
=60
V
REF
Ω
1.16
0.42
0.22
0.22
Min
Ω
.
- 0.15
V
DDQ
256M GDDR3 SDRAM
10pf
60
Ω
)
V
V
V
V
REF
DDQ
DDQ
DDQ
Max
1.36
Rev. 1.3 June 2006
+ 0.15
+ 0.3
+ 0.5
+ 0.3
Unit
V
V
V
V
V
Note
1,2,3
2,4
2
4
3