k4j55323qg Samsung Semiconductor, Inc., k4j55323qg Datasheet - Page 51

• Manufacturer Part Number: k4j55323qg
• Description: 256mbit Gddr3 Sdram
• Manufacturer: Samsung Semiconductor, Inc.

Note :
1. The WRITE latency can be set from 1 to 7 clocks. When the WRITE latency is set to 1 or 2 or 3 clocks(this case can be used regardless of frequency),
2. A low to high transition on the WDQS line is not allowed in the half clock prior to the write preamble.
3. The last rising edge of WDQS after the write postamble must be riven high by the controller. WDQS can not be pulled high by the on-die termination
4. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage
5. The cycle to cycle jitter over 1~6 cycle short term jitter
10.6 AC CHARACTERISTICS(I-I)
K4J55323QG
DQS out access time from CK
CK high-level width
CK low-level width
CK cycle time
WRITE Latency
DQ and DM input hold time relative to DQS
DQ and DM input setup time relative to DQS
Active termination setup time
Active termination hold time
DQS input high pulse width
DQS input low pulse widthl
Data strobe edge to Dout edge
DQS read preamble
DQS read postamble
Write command to first DQS latching transition
DQS write preamble
DQS write preamble setup time
DQS write postamble
Half strobe period
Data output hold time from DQS
Data-out high-impedance window
from CK and /CK
Data-out low-impedance window from
CK and /CK
Address and control input hold time
Address and control input setup time
Address and control input pulse width
Jitter over 1~6 clock cycle error
Cycle to cyde duty cycle error
Rise and fall times of CK
the input buffers are turned on during the ACTIVE commands reducing the latency but added power. When the WRITE latency is set to 4 ~7 clocks ,
the input buffers are turned on during the WRITE commands for lower power operation. The WRITE latency which is over 4 clocks can be used only in
case that Write Latency*tCK is greater than 7ns.
alone.
level, but specify when the device output is no longer driving (HZ) or begins driving (LZ).
Parameter
CL=11
CL=10
CL=9
CL=8
CL=7
Symbol
tWPRES
tDCERR
tDQSQ
tWPRE
t
tDQSH
tRPRE
tDQSS
tWPST
tDQSL
tRPST
DQSCK
tR, tF
tIPW
t
t
tHP
tQH
tHZ
t
t
t
t
t
tLZ
t
ATH
tIH
tIS
ATS
CH
CK
WL
DH
DS
tJ
CL
tCHmin
WL-0.2 WL+0.2 WL-0.2 WL+0.2
tCLmin
-0.140
-0.23
Min
0.45
0.45
1.25
0.16
0.16
0.48
0.48
0.35
0.14
-0.3
-0.3
t
1.4
1.6
2.0
2.0
0.4
0.4
0.4
0.3
0.3
0.9
HP
10
10
or
6
0
-
-
-
-
-12
- 51 /53 -
+0.23
0.140
Max
0.55
0.55
0.52
0.52
0.03
0.03
3.3
0.6
0.6
0.6
0.2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
tCHmin
tCLmin
-0.160
-0.26
Min
0.45
0.45
0.18
0.18
0.48
0.48
0.16
0.35
0.35
t
-0.3
-0.3
1.4
1.6
2.0
2.0
0.4
0.4
0.4
0.4
1.0
HP
10
10
or
5
0
-
-
-
-
-14
+0.26
0.160
Max
0.55
0.55
0.52
0.52
0.03
0.03
3.3
0.6
0.6
0.6
0.6
0.2
-
-
-
-
-
-
-
-
-
-
-
-
-
tCHmin
tCLmin
WL-0.2
0.180
-0.29
0.45
0.45
0.20
0.20
0.48
0.48
0.18
Min
t
-0.3
-0.3
1.6
2.0
2.0
0.4
0.4
0.4
0.4
0.4
0.4
1.1
10
10
HP
or
5
0
-
-
-
-
-
-
256M GDDR3 SDRAM
-16
WL+0.2
+0.29
0.180
Max
0.55
0.55
0.52
0.52
0.03
0.03
3.3
0.6
0.6
0.6
0.6
0.2
-
-
-
-
-
-
-
-
-
-
-
-
-
Rev. 1.3 June 2006
tCHmin
tCLmin
0.225
WL-0.2
0.225
-0.35
0.45
0.45
0.25
0.25
0.48
0.48
-0.3
-0.3
Min
t
2.0
0.4
0.4
0.4
0.4
0.5
0.5
1.3
10
10
HP
or
4
0
-
-
-
-
-
-
-
-
-20
WL+0.2
+0.35
0.225
Max
0.55
0.55
0.52
0.52
0.03
0.03
3.3
0.6
0.6
0.6
0.6
0.2
-
-
-
-
-
-
-
-
-
-
-
-
-
Unit
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
1
2
3
4
4
5