ADC1443D125HD IDT [Integrated Device Technology], ADC1443D125HD Datasheet - Page 13

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ADC1443D125HD

Manufacturer Part Number
ADC1443D125HD
Description
Dual channel 14-bit ADC; 125, 160 or 200 Msps; JESD204B serial outputs
Manufacturer
IDT [Integrated Device Technology]
Datasheet
Integrated Device Technology
ADC1443D_SER
Objective data sheet
10.2.1 Clock timing
10.2.2 SYSREF timing
10.2 Timing
Table 7.
[1]
Table 8.
Symbol Parameter
t
t
Clock timing
f
f
t
Symbol
t
t
d(s)
su
lat(data)
wake
s
clk
h
Fig 3.
clk
Typical values measured at V
the full temperature range T
V
INP
 V
Clock and digital output timing
data latency time
wake-up time
sampling rate
clock frequency
clock duty cycle
sampling delay time
INM
Clock and digital output timing characteristics
SYSREF timing
Parameter
set-up time
hold time
= 1 dBFS; unless otherwise specified.
Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs
Rev. 03 — 19 July 2012
amb
DDA
= 40 C to 85 C at V
Conditions
from Power-down mode
from Sleep mode
from high impedance
ADC1443D125
ADC1443D160
ADC1443D200
= V
DDO
Conditions
= 1.8 V; T
amb
DDA
= 25 C. Minimum and maximum values are across
= V
ADC1443D series
DDO
[1]
= 1.8 V; V
Min
<tbd>
<tbd>
Min
-
-
-
-
60
125
160
60
30
-
I(dif)
Typ
-
-
Typ
42
<tbd>
<tbd>
<tbd>
-
-
-
-
-
<tbd>
= 2 V;
© IDT 2012. All rights reserved.
Max
-
-
Max
-
-
-
-
125
160
200
800
70
-
Unit
ns
ns
Unit
clock
cycles
ns
ns
ns
MHz
MHz
MHz
MHz
%
ns
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