ADC1443D125HD IDT [Integrated Device Technology], ADC1443D125HD Datasheet - Page 30

• Manufacturer Part Number: ADC1443D125HD
• Description: Dual channel 14-bit ADC; 125, 160 or 200 Msps; JESD204B serial outputs
• Manufacturer: IDT [Integrated Device Technology]

Integrated Device Technology
Table 16.
[1]
ADC1443D_SER
Objective data sheet
CFG_SETUP[3:0]
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
F: Octets per frame clock cycle
HD: High-density mode
K: Frame per multi-frame
M: Converters per device
L: Lane per converter device
CS: Number of control bits per conversion sample
CF: Control words per frame clock cycle and link
S: Number of samples transmitted per single converter per frame cycle
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
JESD204A/JESD204B configuration table
11.4 Configuration pins (CFG0, CFG1, CFG2, CFG3)
ADC A ADC B
OFF
OFF
OFF
OFF
ON
ON
ON
ON
ON
ON
The configuration pins are only active as inputs at start-up. The values on those pins are
read once to set up the device. Then the pins become outputs (OTRA and OTRB). SPI
applies any change in the configuration.
OFF
OFF
OFF
OFF
ON
ON
ON
ON
ON
ON
Lane 0
OFF
OFF
OFF
OFF
ON
ON
ON
ON
ON
ON
Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs
OFF
Lane 1
Rev. 03 — 19 July 2012
OFF
OFF
OFF
ON
ON
ON
ON
ON
ON
F
2
4
4
2
2
2
2
1
1
2
[1]
HD
0
0
0
0
0
0
0
1
1
0
reserved
reserved
reserved
reserved
reserved
reserved
[1]
K
17
17
9
5
5
9
9
9
9
9
[1]
M
2
2
2
1
1
1
1
1
1
2
[1]
ADC1443D series
L
2
1
1
1
1
1
1
2
2
2
[1]
power-down
(F  K)  17
(F  K)  17
(F  K)  17
(F  K)  17
(F  K)  17
(F  K)  17
(F  K)  17
(F  K)  17
(F  K)  17
Comment
chip
CS
© IDT 2012. All rights reserved.
1
1
1
1
1
1
1
1
1
1
[1]
CF
0
0
0
0
0
0
0
0
0
0
[1]
30 of 49
S
1
1
1
1
1
1
1
1
1
1
[1]