ADC1443D125HD IDT [Integrated Device Technology], ADC1443D125HD Datasheet - Page 45

• Manufacturer Part Number: ADC1443D125HD
• Description: Dual channel 14-bit ADC; 125, 160 or 200 Msps; JESD204B serial outputs
• Manufacturer: IDT [Integrated Device Technology]

Integrated Device Technology
Table 51.
Default settings are shown highlighted.
Table 52.
Default settings are shown highlighted.
Table 53.
Default settings are shown highlighted.
ADC1443D_SER
Objective data sheet
Bit
7 to 5
4 to 3
2
1
0
Bit
7 to 6
5 to 4
3 to 1
0
Bit
7 to 6
5 to 4
3 to 1
0
Symbol
RESERVED[2:0]
LANE_MODE[1:0]
LANE_POL
RESERVED
LANE_PD
Symbol
RESERVED
ADC_MODE[1:0]
RESERVED
ADC_PD
Symbol
RESERVED
ADC_MODE[1:0]
RESERVED
ADC_PD
IP_ADC00_0_CTRL register (address 0890h) bit description
IP_ADC01_0_CTRL register (address 0891h) bit description
IP_LANE01_0_CTRL register (address 0872h) bit description
Access
R/W
R/W
R/W
R/W
R/W
Access
R/W
R/W
R/W
R/W
Access
R/W
R/W
R/W
R/W
Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs
Rev. 03 — 19 July 2012
Value
00
0
0
*
Value
00
000
0
Value
00
000
0
000
00
00
Description
reserved
debug option directly before serializer
if set to logic 1, lane P/N polarity is inverted
reserved
if set to logic 1, lane enters power-down
Description
reserved
debug option to replace ADC core
reserved
if set to logic 1, ADC enters power-down
Description
reserved
debug option to replace ADC core
reserved
if set to logic 1, ADC enters power-down
0: normal mode, ADC path
1: toggle (0/1 toggle sent over the lanes)
2: A constant (value in IP_DEBUG_OUT) is sent
over the lanes
3: PRBS polynom is sent over the lane
0, 1: normal mode, ADC path
2: a constant (value in IP_Debug_in) is sent
instead of ADC conversion output
3: PRBS polynom is sent instead of ADC
0, 1: normal mode, ADC path
2: a constant (value in IP_Debug_in) is sent
instead of ADC conversion output
3: PRBS polynom is sent instead of ADC
ADC1443D series
© IDT 2012. All rights reserved.
45 of 49