ADC1443D125HD IDT [Integrated Device Technology], ADC1443D125HD Datasheet - Page 14

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ADC1443D125HD

Manufacturer Part Number
ADC1443D125HD
Description
Dual channel 14-bit ADC; 125, 160 or 200 Msps; JESD204B serial outputs
Manufacturer
IDT [Integrated Device Technology]
Datasheet
Integrated Device Technology
ADC1443D_SER
Objective data sheet
10.2.3 SPI timing
Table 9.
[1]
Symbol
t
t
t
t
t
f
su
w(SCLK)
w(SCLKH)
w(SCLKL)
h
clk
Fig 4.
Fig 5.
Typical values measured at V
the full temperature range T
SYSREF timing
SPI timing
SCS_N
SPI timing characteristics
SCLK
SDIO
Parameter
SCLK pulse width
SCLK HIGH pulse width
SCLK LOW pulse width
set-up time
hold time
clock frequency
Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs
t
su
R/W
Rev. 03 — 19 July 2012
amb
DDA
= 40 C to +85 C at V
W1
t
= V
h
t
su
DDO
W0
t
[1]
w(SCLK)
= 1.8 V; T
Conditions
SDIO to SCLK HIGH
SCS_N to SCLK HIGH
SDIO to SCLK HIGH
SCS_N to SCLK HIGH
A12
amb
= 25 C. Minimum and maximum values are across
DDA
A11
t
w(SCLKL)
= V
ADC1443D series
t
w(SCLKH)
DDO
D2
= 1.8 V
D1
Min
40
16
16
5
5
2
2
-
D0
Typ
-
-
-
-
-
-
-
-
t
h
001aan454
© IDT 2012. All rights reserved.
Max
-
-
-
-
-
-
25
-
14 of 49
Unit
ns
ns
ns
ns
ns
ns
ns
MHz

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