ADC1443D125HD IDT [Integrated Device Technology], ADC1443D125HD Datasheet - Page 27

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ADC1443D125HD

Manufacturer Part Number
ADC1443D125HD
Description
Dual channel 14-bit ADC; 125, 160 or 200 Msps; JESD204B serial outputs
Manufacturer
IDT [Integrated Device Technology]
Datasheet
Integrated Device Technology
ADC1443D_SER
Objective data sheet
Fig 37. General overview of the JESD204A/JESD204B serializer
Fig 38. Detailed view of the JESD204A/JESD204B serializer with debug functionality
S samples per frame cycle
N bits from Cr
CS bits for control
SYNC~
CS bits for control
N bits from Cr
M CONVERTERS
N' = N+CS
ADC_PD
ADC_PD
DUMMY
DUMMY
ADC A
ADC B
PRBS
PRBS
AND
DLL
PLL
M−1
0
+
+
× 10F
Mx(N'xS) bits
× F
14 + 1
14 + 1
× 1
14 + 1
14 + 1
ADC_MODE[1:0]
ADC_MODE[1:0]
frame CLK
character CLK
bit CLK
lane stream mapping
samples stream to
TX transport layer
10
11
11
10
00
00
HD: frame boundary break
CF: position of control bits
Padding with Tail bits (TT)
14 + 1
14 + 1
AND
AND
CS
CS
ASSEMBLY
N
N
FRAME
L LANES
F octets
F octets
N + CS
N + CS
Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs
Lx(F) octets
Rev. 03 — 19 July 2012
replication;
test mode)
assembly,
OCTETS
OCTETS
character
FRAME
FRAME
(frame
FSM
ILA,
TO
TO
L octets
SCRAMBLER
SCRAMBLER
sync_request
8
8
SCR
SCR
TX CONTROLLER
CHARACTER
GENERATOR
CHARACTER
GENERATOR
ALIGNMENT
ALIGNMENT
ADC1443D series
10-bit
10-bit
8-bit/
8-bit/
LANE_MODE[1:0]
LANE_MODE[1:0]
10
10
LANE_POL
LANE_POL
10-bit
10-bit
8-bit/
8-bit/
SER
SER
005aaa084
aaa-000423
SER
SER
© IDT 2012. All rights reserved.
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