ADC1443D125HD IDT [Integrated Device Technology], ADC1443D125HD Datasheet - Page 21
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ADC1443D125HD
Manufacturer Part Number
ADC1443D125HD
Description
Dual channel 14-bit ADC; 125, 160 or 200 Msps; JESD204B serial outputs
Manufacturer
IDT [Integrated Device Technology]
Datasheet
1.ADC1443D125HD.pdf
(49 pages)
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Integrated Device Technology
ADC1443D_SER
Objective data sheet
11.1.4 Programmable full-scale
11.1.5 Anti-kickback circuitry
The full-scale analog input voltage range is configurable between 1 V (p-p) and 2 V (p-p)
by programming internal reference gain between 0 dB and 6 dB in 1 dB steps. The
full-scale range can be set independently via bits INTREF[2:0] of the SPI local registers
(see Table 10 and Table 24).
Table 10.
Default values are shown highlighted.
An anti-kickback circuitry (RC-filter in Figure 28) is required to counteract the effects of the
The RC-filter is also used to filter noise from the signal before it reaches the sampling
stage. It is recommended that the capacitor has a value that maximizes noise attenuation
without degrading the settling time excessively.
INTREF[2:0]
000
001
010
011
100
101
110
111
Fig 27. Equivalent schematic of the common-mode reference circuit
0.1 μF
Reference gain control
VCM
charge injection generated by the sampling capacitance.
Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs
PACKAGE
Rev. 03 — 19 July 2012
Level (dB)
0
1
2
3
4
5
6
reserved
ESD
PARASITICS
ADC1443D series
COMMON MODE
REFERENCE
Full-scale (V (p-p))
2
1.78
1.59
1.42
1.26
1.12
1
x
ADC CORE
© IDT 2012. All rights reserved.
001aan473
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