ADC1443D125HD IDT [Integrated Device Technology], ADC1443D125HD Datasheet - Page 40

• Manufacturer Part Number: ADC1443D125HD
• Description: Dual channel 14-bit ADC; 125, 160 or 200 Msps; JESD204B serial outputs
• Manufacturer: IDT [Integrated Device Technology]

Integrated Device Technology
Table 33.
Default settings are shown highlighted.
Table 34.
Default settings are shown highlighted.
Table 35.
Default settings are shown highlighted.
ADC1443D_SER
Objective data sheet
Bit
7
6 to 1
0
Bit
7
6 to 4
3
2 to 0
Bit
7 to 4
3 to 0
Symbol
RXSYNC_ERR_FLG
RESERVED[5:0]
PLL_LOCK
Symbol
SW_RST
-
ASSEMBLER_SW_RST
-
Symbol
-
CFG_SETUP[3:0]
IP_STATUS register (address 0801h) bit description
IP_RESET register (address 0802h) bit description
IP_CFG_SETUP register (address 0803h) bit description
11.5.3.2 JESD204A/JESD204B control registers
Table 36.
CFG_SETUP
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
Serial frequency computation information
Access
R
R
R
Access
R/W
-
R/W
-
Access
-
R/W
Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs
ADC sampling
frequency (Mbps)
FS
FS
FS
FS
FS
FS
FS
FS
FS
Rev. 03 — 19 July 2012
Value
000000
Value
000
000
Value
0000
****
0
0
0
0
Description
RX synchronization error
reserved
JEDEC PLL lock
Description
software reset: All JESD subblocks and registers are
reset
not used
Only the RXSYNC_ERR_FLG register bit and the
frame assembler subblock are reset
not used
Description
not used
see Table 37
0: no error
1: synchronization error has occurred
0: unlocked
1: locked
Lane 0 serial
frequency (Gbps)
20  FS
40  FS
0
20  FS
0
20  FS
0
10  FS
10  FS
reserved
reserved
reserved
reserved
ADC1443D series
Lane 1 serial
frequency (Gbps)
20  FS
0
40  FS
0
20  FS
0
20  FS
10  FS
10  FS
© IDT 2012. All rights reserved.
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