ADC1443D125HD IDT [Integrated Device Technology], ADC1443D125HD Datasheet - Page 38

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ADC1443D125HD

Manufacturer Part Number
ADC1443D125HD
Description
Dual channel 14-bit ADC; 125, 160 or 200 Msps; JESD204B serial outputs
Manufacturer
IDT [Integrated Device Technology]
Datasheet
Integrated Device Technology
Table 26.
Default settings are shown highlighted.
[1]
Table 27.
Default settings are shown highlighted.
[1]
Table 28.
Default settings are shown highlighted.
[1]
Table 29.
Default settings are shown highlighted.
[1]
Table 30.
Default settings are shown highlighted.
[1]
Table 31.
Default settings are shown highlighted.
ADC1443D_SER
Objective data sheet
Bit
1 to 0
Bit
7 to 2
1 to 0
Bit
7 to 3
2 to 0
Bit
7 to 0
Bit
7 to 2
1 to 0
Bit
7 to 5
4
Local register
Local register
Local register
Local register
Local register
Symbol
DATA_FORMAT[1:0:]
Symbol
DIG_OFFSET[7:0]
-
Symbol
-
TEST_PAT_SEL[2:0]
Symbol
TEST_PAT_USER[13:6]
Symbol
TEST_PAT_USER[5:0]
-
Symbol
-
RESERVED
OUTPUT_CFG register (address 0011h) bit description
DIG_OFFSET register (address 0013h) bit description
TEST_CFG_1 register (address 0014h) bit description
TEST_CFG_2 register (address 0015h) bit description
TEST_CFG_3 register (address 0016h) bit description
OTR_CFG register (address 0017h) bit description
[1]
[1]
[1]
[1]
[1]
Access
R/W
Access
R/W
-
Access
-
R/W
Access
R/W
Access
R/W
-
Access
-
R/W
Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs
Rev. 03 — 19 July 2012
Value
00
01
10
11
Value
-
-
Value
-
-
Value
-
Value
-
-
Value
-
1
…continued
Description
output data format
Description
see Table 13
not used
Description
not used
see Table 14
Description
custom digital test pattern (bits 13 to 6)
Description
custom digital test pattern (bits 7 to 0)
not used
Description
not used
reserved
offset binary
two’s complement
gray code
offset binary
ADC1443D series
© IDT 2012. All rights reserved.
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