ADC1443D125HD IDT [Integrated Device Technology], ADC1443D125HD Datasheet - Page 28

• Manufacturer Part Number: ADC1443D125HD
• Description: Dual channel 14-bit ADC; 125, 160 or 200 Msps; JESD204B serial outputs
• Manufacturer: IDT [Integrated Device Technology]

Integrated Device Technology
ADC1443D_SER
Objective data sheet
11.3.3 OuT-of-Range (OTR)
11.3.4 Digital offset
An out-of-range signal is provided on pins OTRA and OTRAB.
The latency of OTR is 31 clock cycles. The OTR response can be speeded up by enabling
fast OTR using SPI local registers (bit FAST_OTR in Table 31). In this mode, the latency
of OTR is reduced to only <tbd> clock cycles. The fast OTR detection threshold (below
full-scale) can be programmed using the SPI local registers (bits FAST_OTR_DET[2:0] in
Table 31).
Table 12.
By default, the ADC1443D delivers an output code that corresponds to the analog input.
However, it is possible to add a digital offset to the output code using the SPI local
registers (bits DIG_OFFSET[5:0] in see Table 13 and Table 27). The digital offset
adjustment is coded in two’s complement.
Table 13.
Default values are shown highlighted.
FAST_OTR_DET[2:0]
000
001
010
011
100
101
110
111
DIG_OFFSET[5:0]
10 0000
10 0001
...
11 1111
00 0000
00 0001
...
01 1110
01 1111
Fast OTR register threshold
Digital offset adjustment
Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs
Rev. 03 — 19 July 2012
Detection level (dB)
18.06
14.54
12.04
8.52
6.02
4.08
2.5
1.16
Digital offset adjustment (LSB)
32
31
...
1
0
+1
...
+30
+31
ADC1443D series
© IDT 2012. All rights reserved.
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