ADC1443D125HD IDT [Integrated Device Technology], ADC1443D125HD Datasheet - Page 41

• Manufacturer Part Number: ADC1443D125HD
• Description: Dual channel 14-bit ADC; 125, 160 or 200 Msps; JESD204B serial outputs
• Manufacturer: IDT [Integrated Device Technology]

Integrated Device Technology
Table 37.
[1]
Table 38.
Default settings are shown highlighted.
ADC1443D_SER
Objective data sheet
CFG_SETUP[3:0]
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Bit
7
6
F: Octets per frame clock cycle
HD: High-density mode
K: Frame per multi-frame
M: Converters per device
L: Lane per converter device
CS: Number of control bits per conversion sample
CF: Control words per frame clock cycle and link
S: Number of samples transmitted per single converter per frame cycle
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Symbol
RESERVED
TRISTATE_CFG_PAD
JESD204A/JESD204B configuration table
IP_CTRL1 register (address 0805h) bit description
ADC[0] ADC[1] Lane 0
OFF
OFF
OFF
OFF
ON
ON
ON
ON
ON
ON
Table 36.
CFG_SETUP
1101
1110
1111
OFF
OFF
OFF
OFF
ON
ON
ON
ON
ON
ON
Serial frequency computation information
Access
R/W
R/W
OFF
OFF
OFF
OFF
ON
ON
ON
ON
ON
ON
Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs
ADC sampling
frequency (Mbps)
FS
Lane 1
Rev. 03 — 19 July 2012
OFF
OFF
OFF
OFF
ON
ON
ON
ON
ON
ON
Value
0
(1 > 0)
F
2
4
4
2
2
2
2
1
1
2
[1]
HD
reserved
reserved
reserved
reserved
reserved
reserved
0
0
0
0
0
0
0
1
1
0
[1]
Description
reserved
TriState configuration pad
K
0: CFG Pads in Output mode (debug feature)
1: CFG Pads in Input mode; operating at
power-up (see Table 37)
17
17
9
5
5
9
9
9
9
9
[1]
Lane 0 serial
frequency (Gbps)
0
M
2
2
1
1
1
2
2
1
1
1
[1]
reserved
reserved
ADC1443D series
L
2
1
1
1
1
1
1
2
2
2
[1]
power-down
(F  K)  17
(F  K)  17
(F  K)  17
(F  K)  17
(F  K)  17
(F  K)  17
(F  K)  17
(F  K)  17
(F  K)  17
Comment
chip
Lane 1 serial
frequency (Gbps)
0
1
CS
© IDT 2012. All rights reserved.
1
1
1
1
1
1
1
1
1
[1]
CF
0
0
0
0
0
0
0
0
0
0
[1]
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S
1
1
1
1
1
1
1
1
1
1
[1]